Instruction
MOVQ
Moves 64 bits between MMX or XMM registers, general-purpose registers and memory, zeroing the rest of an XMM destination.
MOVQ moves 64 bits, and under one name it gathers three jobs with different opcodes:
| Encoding | Moves |
|---|---|
| 66 REX.W 0F 6E, 66 REX.W 0F 7E | between an XMM register and a 64-bit general-purpose register (or memory) |
| F3 0F 7E | into an XMM register, from memory or from another XMM register |
| 66 0F D6 | out of an XMM register, to memory or to another XMM register |
Into an XMM register, bits 127:64 become zero and the legacy form keeps
bits 128 and up; VMOVQ clears those too. A
register-to-register MOVQ is therefore not a copy: it keeps the low
quadword and clears the high one, which is what _mm_move_epi64 asks
for. Zen 5 recorded movq xmm4, xmm4 doing just that.
MOVSD between registers differs on this point and keeps
the destination’s upper half.
Which encoding
GNU as 2.44 picks F3 0F 7E for loads and register copies, 66 0F D6 for
stores, and the REX.W forms only for general-purpose registers. The
REX.W forms with a memory operand also exist, a byte longer, and moved
the same eight bytes when Zen 5 ran them. AMD’s manual files the
general-purpose forms under MOVD, and its MOVQ page lists only F3 0F 7E
and 66 0F D6. In AT&T syntax, movq is also the ordinary 64-bit
MOV, as in movq %rax, %rbx; only an %xmm or %mm
operand makes it this instruction.
In compiled code
GCC 14 and Clang 23 at -O2 emit it for _mm_cvtsi64_si128,
_mm_cvtsi128_si64 and _mm_move_epi64, for the bits of a double
copied into a uint64_t with memcpy, and twice, before a
PUNPCKLQDQ, for _mm_set_epi64x(a, b). For
_mm_loadl_epi64 and _mm_storel_epi64 GCC uses MOVQ, while Clang
loads with MOVSD and stores with MOVLPS.
Intel’s optimization manual recommends MOVQ or MOVSD for 64-bit loads, which write the whole register instead of merging into it as MOVLPD does (Section 3.5.2.4). It also shows a forwarding trap: a MOVQ load of eight bytes just written by two 32-bit stores cannot take its data from them, and waits until they are written (Section 6.7.1).
The MMX forms (0F 6F and 0F 7F, and 0F 6E and 0F 7E with REX.W) change the x87 state as MOVD explains. AMD’s Zen 5 guide lists the legacy MOVQ from a general-purpose register as two macro-ops, against one for VMOVQ.
Forms
| Instruction | Encoding | Requires |
|---|---|---|
MOVQ xmm, r64 64-bit mode only
MOVQ_XMMdq_GPR64 | 66 REX.W 0F 6E /r | SSE2 |
MOVQ r64, xmm 64-bit mode only
MOVQ_GPR64_XMMq | 66 REX.W 0F 7E /r | SSE2 |
MOVQ xmm, xmm
MOVQ_XMMdq_XMMq_0FD6 | 66 0F D6 /r | SSE2 |
MOVQ xmm, xmm
MOVQ_XMMdq_XMMq_0F7E | F3 0F 7E /r | SSE2 |
MOVQ xmm, m64 64-bit mode only
MOVQ_XMMdq_MEMq_0F6E | 66 REX.W 0F 6E /r | SSE2 |
MOVQ m64, xmm 64-bit mode only
MOVQ_MEMq_XMMq_0F7E | 66 REX.W 0F 7E /r | SSE2 |
MOVQ xmm, m64
MOVQ_XMMdq_MEMq_0F7E | F3 0F 7E /r | SSE2 |
MOVQ m64, xmm
MOVQ_MEMq_XMMq_0FD6 | 66 0F D6 /r | SSE2 |
MOVQ mm, m64 64-bit mode only
MOVQ_MMXq_MEMq_0F6E | REX.W 0F 6E /r | MMX |
MOVQ mm, r64 64-bit mode only
MOVQ_MMXq_GPR64 | REX.W 0F 6E /r | MMX |
MOVQ m64, mm 64-bit mode only
MOVQ_MEMq_MMXq_0F7E | REX.W 0F 7E /r | MMX |
MOVQ r64, mm 64-bit mode only
MOVQ_GPR64_MMXq | REX.W 0F 7E /r | MMX |
MOVQ mm, m64
MOVQ_MMXq_MEMq_0F6F | NP 0F 6F /r | MMX |
MOVQ mm, mm
MOVQ_MMXq_MMXq_0F6F | NP 0F 6F /r | MMX |
MOVQ m64, mm
MOVQ_MEMq_MMXq_0F7F | NP 0F 7F /r | MMX |
MOVQ mm, mm
MOVQ_MMXq_MMXq_0F7F | NP 0F 7F /r | MMX |
Data flow
Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.
MOVQ mm, r/m64 64-bit mode only MOVQ xmm, r/m64 64-bit mode onlyResult quadwords 1 to 0: 0, a0.
MOVQ r/m64, mm 64-bit mode only MOVQ r/m64, xmm 64-bit mode onlyr64 receives quadword 0 of xmm2: a0.
MOVQ mm, mm MOVQ xmm, xmmResult quadwords 1 to 0: 0, a0.
Operation
What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.
MOVQ xmm, r/m64 64-bit mode onlyxmm1.write(src2.q[0]) # bits 127:64 zeroed
# bits 128 and up of the register are unchangedRun on AMD Zen 5 (EPYC 9645): 3 cases.
MOVQ r/m64, xmm 64-bit mode onlydest.write(xmm2.q[0])Run on AMD Zen 5 (EPYC 9645): 3 cases.
MOVQ xmm, xmmxmm1.write(xmm2.q[0]) # bits 127:64 zeroed
# bits 128 and up of the register are unchangedRun on AMD Zen 5 (EPYC 9645): 2 cases.
MOVQ mm, r/m64 64-bit mode onlymm1.write(src2.q[0])
# x87: TOP = 0, all tags valid, bits 79:64 of mm1's register all onesRun on AMD Zen 5 (EPYC 9645): 3 cases.
MOVQ r/m64, mm 64-bit mode onlydest.write(mm2.q[0])
# x87: TOP = 0, all tags validRun on AMD Zen 5 (EPYC 9645): 3 cases.
MOVQ mm, mmmm1.write(mm2.q[0])
# x87: TOP = 0, all tags valid, bits 79:64 of mm1's register all onesRun on AMD Zen 5 (EPYC 9645): 2 cases.
Operands
| Operand | Kind | Action |
|---|---|---|
MOVQ xmm, r/m64 64-bit mode only MOVQ xmm, xmm/m64 | ||
xmm | explicit | write |
r/m64, xmm/m64 | explicit | read |
MOVQ r/m64, xmm 64-bit mode only MOVQ xmm/m64, xmm | ||
r/m64, xmm/m64 | explicit | write |
xmm | explicit | read |
MOVQ mm, r/m64 64-bit mode only MOVQ mm, mm/m64 | ||
mm | explicit | write |
r/m64, mm/m64 | explicit | read |
MOVQ r/m64, mm 64-bit mode only MOVQ mm/m64, mm | ||
r/m64, mm/m64 | explicit | write |
mm | explicit | read |
Flags
None: XED records no flag that the forms test or change.
Exceptions
The exception class is XED's name for the set of exception conditions that a form follows. How to read.
MOVQ xmm, r/m6464-bit mode onlyMOVQ r/m64, xmm64-bit mode onlyMOVQ xmm, xmm/m64MOVQ xmm/m64, xmmSSE_TYPE_5MOVQ mm, r/m6464-bit mode onlyMOVQ r/m64, mm64-bit mode onlyMOVQ mm, mm/m64MOVQ mm/m64, mmmmx-nofp2
Attributes
What else XED records about the forms. How to read.
MOVQ mm, r/m6464-bit mode onlyMOVQ r/m64, mm64-bit mode onlyMOVQ mm, mm/m64MOVQ mm/m64, mm- may abort a TSX transaction
Intrinsics
The C intrinsics of Clang 23.1.2 that compile to MOVQ, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.
| Intrinsic | Compiles to |
|---|---|
_castf64_u64
unsigned long long _castf64_u64(double __A) |
|
_castu64_f64
double _castu64_f64(unsigned long long __A) |
|
_mm_cvtm64_si64
long long _mm_cvtm64_si64(__m64 __m) |
|
_mm_cvtsi128_si64
long long _mm_cvtsi128_si64(__m128i __a) |
|
_mm_cvtsi64_m64
__m64 _mm_cvtsi64_m64(long long __i) |
|
_mm_cvtsi64_si128
__m128i _mm_cvtsi64_si128(long long __a) |
|
_mm_loadl_epi64
__m128i _mm_loadl_epi64(const __m128i_u *__p) |
|
_mm_loadu_si64
__m128i _mm_loadu_si64(const void *__a) |
|
_mm_move_epi64
__m128i _mm_move_epi64(__m128i __a) |
|
_mm_set_sd
__m128d _mm_set_sd(double __w) |
|
_mm_storeu_si64
void _mm_storeu_si64(void *__p, __m128i __b) |
|
CPUID and processors
Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.
More SSE2 instructions
- DIVPD
- DIVSD
- LFENCE
- MASKMOVDQU
- MAXPD
- MAXSD
- MFENCE
- MINPD
- MINSD
- MOVAPD
- MOVD
- MOVDQ2Q
- MOVDQA
- MOVDQU
- MOVHPD
- MOVLPD
- MOVMSKPD
- MOVNTDQ
- MOVNTI
- MOVNTPD
- MOVQ2DQ
- MOVSD
- MOVUPD
- MULPD
- MULSD
- ORPD
- PACKSSDW
- PACKSSWB
- PACKUSWB
- PADDB
- PADDD
- PADDQ
- PADDSB
- PADDSW
- PADDUSB
- PADDUSW
- PADDW
- PAND
- PANDN
- PAVGB
More MMX instructions
Sources
- Intel XED v2026.08.23 (commit
0bcb6237345c): forms, encodings, operands, flags, exception classes, attributes, ISA sets, CPUID bits and chip model. - The CPU data of x86-64.net: Zen 3 to Zen 6, from GCC’s
-marchfeature sets and AMD’s Processor Programming References, which the page of each processor cites. - Clang's x86 intrinsic headers, LLVM 23.1.2 (commit
85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them. - Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026): Volume 2B, page 4-54 (MOVD/
MOVQ) ; Volume 2B, page 4-99 (MOVQ) - Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 1 (253665-093, September 2026)
- AMD64 Architecture Programmer's Manual, Volume 4: 128-Bit and 256-Bit Media Instructions (26568, rev. 3.25, November 2021), Wayback Machine copy of AMD's PDF
- Intel 64 and IA-32 Architectures Optimization Reference Manual, Volume 1 (248966-051, October 2026)
- Software Optimization Guide for the AMD Zen5 Microarchitecture (58455, rev. 1.00, August 2024), Wayback Machine copy of AMD's ZIP
The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang, part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.