x86-64.net

Instruction

MOVRS

Loads a register from memory with a hint that other cores are likely to read the same data before it is written.

Extensions
Forms
4 (2 Legacy, 2 EVEX)
Data
Intel XED v2026.08.23

Forms

Every encoding of MOVRS that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
MOVRS r32, m32 64-bit mode only MOVRS_GPRv_MEMv0F 38 8B /rMOVRS
MOVRS r8, m8 64-bit mode only MOVRS_GPR8i8_MEMi80F 38 8A /rMOVRS
MOVRS r16/32/64, m16/32/64 MOVRS_GPRv_MEMv_APXEVEX.LLZ.NP.MAP4.SCALABLE 8B /rAPX_F + MOVRS
MOVRS r8, m8 MOVRS_GPR8i8_MEMi8_APXEVEX.LLZ.NP.MAP4.W0 8A /rAPX_F + MOVRS

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to MOVRS, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

IntrinsicCompiles to
_movrs_i16 short _movrs_i16(const void *__A)

MOVRS r32, m32 Legacy -mmovrs

_movrs_i32 int _movrs_i32(const void *__A)

MOVRS r32, m32 Legacy -mmovrs

_movrs_i64 long long _movrs_i64(const void *__A)

MOVRS r32, m32 Legacy -mmovrs

_movrs_i8 char _movrs_i8(const void *__A)

MOVRS r8, m8 Legacy -mmovrs

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, which covers AMD processors up to Zen 2.
ISA setCPUIDProcessors in XED
MOVRS

MOVRS
CPUID.(EAX=07H,ECX=1):EAX[31] MOVRS

Nova Lake, Diamond Rapids
APX_F_MOVRS

APX_F + MOVRS
CPUID.(EAX=07H,ECX=1):EDX[21] APX_F
CPUID.(EAX=07H,ECX=1):EAX[31] MOVRS

Nova Lake, Diamond Rapids

More MOVRS instructions

More APX instructions

All 88 APX instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model.
  2. Clang's x86 intrinsic headers, LLVM 23.1.2 (commit 85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them.
  3. Intel Architecture Instruction Set Extensions and Future Features Programming Reference (319433-062, June 2026)
  4. Intel Advanced Performance Extensions (Intel APX) Architecture Specification, revision 7.0 (July 2025)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang, part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.