MOVRS instruction (MOVRS, APX)

MOVRS loads a general-purpose register from memory as MOV does, a byte, word, doubleword or quadword, and adds the read-shared hint: the data is expected to be read by other cores before anyone writes it. The register gets the same value as from an ordinary load, so MOVRS can replace one wherever the hint fits; what the hint asks of the caches, and what it costs a later write, is on the page of VMOVRSD, the vector form.

Its encoding

MOVRS has only the load direction, with a memory source: opcode 0F38 8A for the byte form and 0F38 8B for the others, with 66 or REX.W for the word and quadword sizes. It exists only in 64-bit mode, and a LOCK, F2 or F3 prefix makes it raise #UD, as does a clear MOVRS bit, CPUID.(EAX=07H,ECX=1):EAX[31]. APX adds an EVEX form for its new registers. PREFETCHRST2 brings a line into the caches with the same hint and no register written; Intel lists both for Diamond Rapids and Nova Lake.

In our builds and on Zen 5

GCC 14 has no -mmovrs. Clang 23 turns it on for -march=diamondrapids and -march=novalake, and with -mmovrs at -O2 compiles _movrs_i8 to _movrs_i64 to movrs al, byte ptr [rdi] up to movrs rax, qword ptr [rdi]. A loop summing long long values read with _movrs_i64 stays scalar, unrolled eight times, each value loaded by a MOVRS and then added in a second instruction, since MOVRS cannot serve as the memory operand of an ADD; the same loop with plain loads becomes MOVDQU and PADDQ, two values at a time. The Zen 5 behind this site’s recorded cases reports 30h in that leaf’s EAX, without bit 31, and both cases, movrs ecx, dword ptr [0x10000004] and the byte form, raised #UD.

Forms

Every encoding of MOVRS that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`MOVRS r16/32/64, m16/32/64` 64-bit mode only MOVRS_GPRv_MEMv	`0F 38 8B /r`	MOVRS
`MOVRS r8, m8` 64-bit mode only MOVRS_GPR8i8_MEMi8	`0F 38 8A /r`	MOVRS
`MOVRS r16/32/64, m16/32/64` MOVRS_GPRv_MEMv_APX	`EVEX.LLZ.NP.MAP4.SCALABLE 8B /r`	APX_F + MOVRS
`MOVRS r8, m8` MOVRS_GPR8i8_MEMi8_APX	`EVEX.LLZ.NP.MAP4.W0 8A /r`	APX_F + MOVRS

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

if not cpuid_leaf(7, 1)[0] >> 31 & 1:
    fault(UD)                    # CPUID: no MOVRS
dest.write(src)                  # as MOV, with a hint that other processors
                                 # are likely to read the line before it is
                                 # written

Run on AMD Zen 5 (EPYC 9645): 2 cases. Its cases ran where CPUID reported no MOVRS, and every one raised an exception. The APX forms were not run: none of these processors has APX.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`MOVRS r8, m8` 64-bit mode only `MOVRS r16/32/64, m16/32/64` 64-bit mode only
`r8/16/32/64`	explicit	write
`m8/16/32/64`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

Legacy forms: LEGACY-MOVRS
EVEX forms: APX-EVEX-MOVRS

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to MOVRS, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`_movrs_i16` `short _movrs_i16(const void *__A)`	`MOVRS r16/32/64, m16/32/64` Legacy -mmovrs
`_movrs_i32` `int _movrs_i32(const void *__A)`	`MOVRS r16/32/64, m16/32/64` Legacy -mmovrs
`_movrs_i64` `long long _movrs_i64(const void *__A)`	`MOVRS r16/32/64, m16/32/64` Legacy -mmovrs
`_movrs_i8` `char _movrs_i8(const void *__A)`	`MOVRS r8, m8` Legacy -mmovrs

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`MOVRS` MOVRS	MOVRS `CPUID.(EAX=07H,ECX=1):EAX[31]` MOVRS	Nova Lake, Diamond Rapids
`APX_F_MOVRS` APX	APX_F + MOVRS `CPUID.(EAX=07H,ECX=1):EDX[21]` APX_F `CPUID.(EAX=07H,ECX=1):EAX[31]` MOVRS	Same as `MOVRS`

More MOVRS instructions

More APX instructions

All 88 APX instructions

Its encoding#

In our builds and on Zen 5#