x86-64.net

Instruction

MOVS

Copies the element at [RSI] to [RDI] and steps both pointers; REP MOVS copies RCX elements, the classic memcpy.

Extensions
Mnemonics
MOVS, MOVSB, MOVSW, MOVSD, MOVSQ
Forms
8 (8 Legacy)
Data
Intel XED v2026.08.23

Forms

Every encoding of MOVS that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
MOVSB MOVSBA4Base instruction set
MOVSW MOVSW66 A5Base instruction set
MOVSD MOVSDA5Base instruction set
MOVSQ 64-bit mode only MOVSQREX.W A5LM
REP MOVSB REP_MOVSBF3 A4
F2 A4		Base instruction set
REP MOVSW REP_MOVSW66 F3 A5
66 F2 A5		Base instruction set
REP MOVSD REP_MOVSDF3 A5
F2 A5		Base instruction set
REP MOVSQ 64-bit mode only REP_MOVSQF3 REX.W A5
F2 REX.W A5		LM

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, which covers AMD processors up to Zen 2.
ISA setCPUIDProcessors in XED
I86

No CPUID bit: part of the base instruction set.

Every x86-64 processor in XED’s model
I386

No CPUID bit: part of the base instruction set.

Every x86-64 processor in XED’s model
LONGMODE

LM
CPUID.80000001H:EDX[29] LM

Every x86-64 processor in XED’s model

More General-purpose instructions

All 109 General-purpose instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model.
  2. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-092, June 2026)
  3. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The text is our own.