MOVSD instruction (SSE2)

MOVSD moves one double, the low 64 bits of an XMM register. It is SSE2’s scalar move, and it shares its name with the doubleword form of the string instruction MOVS; assemblers tell the two apart by their operands. What it does to the rest of the register depends on where the double comes from:

From memory it fills the whole XMM register: the double goes to bits 63:0 and bits 127:64 become zero. Zen 5’s recorded load did so and left bits 511:128 as they were, as every legacy SSE instruction does.
To memory it writes eight bytes and nothing else; the recorded store left the bytes after them alone.
Between registers it replaces only bits 63:0 of the destination and keeps bits 127:64, so the old destination is an input. There are two encodings for this, 0F 10 and 0F 11, which GNU as picks with its {load} and {store} prefixes; both recorded cases kept the high double.

No form converts or rounds anything, so MXCSR plays no part, and the memory operand need not be aligned. MOVSS is the same instruction for singles, MOVQ the move that clears the high half even from a register, and VMOVSD the VEX and EVEX form, which merges with a second source rather than with the destination.

In compiled code

In our builds at -O2, GCC 14 and Clang 23 load and store double values with it. A plain copy of a double between registers uses another instruction: GCC uses MOVAPD and Clang MOVAPS, which write the whole register. Intel’s optimization guide recommends that choice, since a register-to-register move waits for whatever last wrote its destination, while a load from memory breaks that dependence (Sections 3.5.2.4 and 3.5.2.6). The register form appears when merging is the point, for _mm_move_sd or storing into element 0 of a __m128d; with -march=x86-64-v2, Clang writes those as BLENDPS with an immediate of 3, and GCC keeps the merging move. For _mm_load_sd, GCC loads with MOVQ and Clang with this instruction, to the same result.

In the optimization guide

What the optimization guide says about MOVSD, a line per claim. Each links to the claim in the guide, with its sources and where they differ.

Out of order

Partial register and flag writes: Scalar SSE instructions that write only the low element of an XMM register keep the rest of it, and so wait for its last writer: movss and movsd between registers, movlpd and movhpd from memory, and conversions and square roots such as cvtsi2sd and sqrtss.

Forms

Every encoding of MOVSD that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`MOVSD xmm, m64` MOVSD_XMM_XMMdq_MEMsd	`F2 0F 10 /r`	SSE2
`MOVSD m64, xmm` MOVSD_XMM_MEMsd_XMMsd	`F2 0F 11 /r`	SSE2
`MOVSD xmm, xmm` MOVSD_XMM_XMMsd_XMMsd_0F10	`F2 0F 10 /r`	SSE2
`MOVSD xmm, xmm` MOVSD_XMM_XMMsd_XMMsd_0F11	`F2 0F 11 /r`	SSE2

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

The double in m64 goes to the low end of xmm1, and the rest of xmm1 is zeroed.MOVSD xmm, m64

Result doubles 1 to 0: 0, a0.

The low double of xmm2 goes to m64.MOVSD m64, xmm

m64 receives double 0 of xmm2: a0.

The low double of xmm2 goes to the low end of xmm1; the others stay as they were.Register forms

Result doubles 1 to 0: unchanged, a0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

MOVSD xmm, m64

xmm1.write(mem.q[0])  # bits 127:64 zeroed
# bits 128 and up of the register are unchanged

Run on AMD Zen 5 (EPYC 9645): 1 case.

MOVSD m64, xmm

mem.q[0] = xmm2.q[0]

Run on AMD Zen 5 (EPYC 9645): 1 case.

xmm1.q[0] = xmm2.q[0]  # the others keep their values
# bits 128 and up of the register are unchanged

Run on AMD Zen 5 (EPYC 9645): 2 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`MOVSD xmm, xmm/m64`
`xmm`	explicit	write
`xmm/m64`	explicit	read
`MOVSD xmm/m64, xmm`
`xmm/m64`	explicit	write
`xmm`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms: SSE_TYPE_5

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to MOVSD, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`_mm_load_sd` `__m128d _mm_load_sd(const double *__dp)`	`MOVSD xmm, m64` Legacy -msse2

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`SSE2` SSE2	SSE2 `CPUID.01H:EDX[26]` SSE2	Every x86-64 processor in XED’s model and Zen 3 to Zen 6

More SSE2 instructions

All 124 SSE2 instructions

In compiled code#