Extensions
Forms
2 (2 Legacy)
Data
Intel XED v2026.08.23

MOVSHDUP copies the odd singles of its source over the even ones: the result is elements 1, 1, 3 and 3. MOVSLDUP repeats the even ones instead, and MOVDDUP a double; all three came with SSE3, beyond the first x86-64 level, and VMOVSHDUP does the same over every pair of a wider register. Unlike MOVDDUP, which reads eight bytes from anywhere, the memory form reads all 16 bytes and needs them aligned to 16. The result keeps bits 128 and up of the register (see SSE and AVX), and a NaN or denormal is copied as it is.

Zen 5’s recorded movshdup xmm12, xmmword ptr [mem] gave bytes 4 to 7 of memory in elements 0 and 1 and bytes 12 to 15 in elements 2 and 3, and the register form did the same with XMM6.

Uses

  • Element 1 to element 0, without a copy. It writes a separate register, so it replaces the MOVAPS and SHUFPS pair that otherwise brings element 1 down. In our builds at -O2 with -march=x86-64-v2, Clang 23 starts a sum of the four floats of a vector with MOVSHDUP and ADDSS, and takes the imaginary part of a float complex returned in XMM0 with movshdup xmm5, xmm0.
  • Complex products. With -fcx-limited-range, GCC 14 multiplies two float complex values with MOVSLDUP and MOVSHDUP, which spread the real and the imaginary part of the first, SHUFPS with E1h, which swaps the parts of the second, two MULPS and an ADDSUBPS, the single-precision pattern of ADDSUBPD.
  • As a shuffle. Both compilers emit it for __builtin_shufflevector(v, v, 1, 1, 3, 3) with SSE3 available; for the default target the same shuffle is shufps xmm0, xmm0, 245.

Forms

Every encoding of MOVSHDUP that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
MOVSHDUP xmm, m128 MOVSHDUP_XMMps_MEMpsF3 0F 16 /rSSE3
MOVSHDUP xmm, xmm MOVSHDUP_XMMps_XMMpsF3 0F 16 /rSSE3

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Duplicate: each odd single is copied into the even place below it.
MOVSHDUPResult singles 3 to 0: a3, a3, a1, a1.0213xmm2or m128aa1a1a3a3xmm1

Result singles 3 to 0: a3, a3, a1, a1.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(4):
    j = i - i % 2 + 1
    xmm1.d[i] = src2.d[j]
# bits 128 and up of the register are unchanged

Run on AMD Zen 5 (EPYC 9645): 2 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.
OperandKindAction
MOVSHDUP xmm, xmm/m128
xmmexplicitwrite
xmm/m128explicitread

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms
SSE_TYPE_4

Attributes

What else XED records about the forms. How to read.

Memory forms
aligned memory operand

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to MOVSHDUP, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

IntrinsicCompiles to
_mm_movehdup_ps __m128 _mm_movehdup_ps(__m128 __a)

MOVSHDUP xmm, xmm Legacy -msse3

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.
ISA setCPUIDProcessors
SSE3

SSE3
CPUID.01H:ECX[0] SSE3

Every x86-64 processor in XED’s model and Zen 3 to Zen 6

More SSE3 instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, operands, flags, exception classes, attributes, ISA sets, CPUID bits and chip model.
  2. The CPU data of x86-64.net: Zen 3 to Zen 6, from GCC’s -march feature sets and AMD’s Processor Programming References, which the page of each processor cites.
  3. Clang's x86 intrinsic headers, LLVM 23.1.2 (commit 85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them.
  4. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026): Volume 2B, page 4-111 (MOVSHDUP)
  5. AMD64 Architecture Programmer's Manual, Volume 4: 128-Bit and 256-Bit Media Instructions (26568, rev. 3.25, November 2021), Wayback Machine copy of AMD's PDF

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang, part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.