Extensions
Forms
2 (2 Legacy)
Data
Intel XED v2026.08.23

MOVSLDUP copies the even singles of its source over the odd ones: the result is elements 0, 0, 2 and 2. It is the twin of MOVSHDUP, whose page covers what the two share: SSE3, a memory operand of 16 bytes that must be aligned, unlike MOVDDUP’s eight, bits 128 and up of the register kept (see SSE and AVX), and no floating-point operation, so NaNs and denormals pass through as bits. VMOVSLDUP is the VEX and EVEX form.

Zen 5’s recorded cases follow the pattern: movsldup xmm12, xmmword ptr [mem] put bytes 0 to 3 of memory in elements 0 and 1 and bytes 8 to 11 in elements 2 and 3, and movsldup xmm7, xmm11 repeated elements 0 and 2 of XMM11.

The real parts of complex floats

An array of float complex keeps each real part in an even element and each imaginary part in the odd one after it, so MOVSLDUP spreads the real parts across their pairs and MOVSHDUP the imaginary ones. That is the first step of a complex product: in our builds at -O2 with -march=x86-64-v2 -fcx-limited-range, GCC 14 compiles r[i] = a[i] * b[i] on float complex values to MOVSLDUP and MOVSHDUP of a[i], each multiplied by b[i] or its swapped parts, and an ADDSUBPS to combine them. Without the option, C’s rules about infinities and NaNs make both GCC and Clang 23 keep the product scalar with a call to __mulsc3 for the rare cases.

As a plain shuffle, __builtin_shufflevector(v, v, 0, 0, 2, 2) is MOVSLDUP in both compilers once SSE3 is enabled, and shufps xmm0, xmm0, 160 for the default target.

Forms

Every encoding of MOVSLDUP that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
MOVSLDUP xmm, m128 MOVSLDUP_XMMps_MEMpsF3 0F 12 /rSSE3
MOVSLDUP xmm, xmm MOVSLDUP_XMMps_XMMpsF3 0F 12 /rSSE3

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Duplicate: each even single is copied into the odd place above it.
MOVSLDUPResult singles 3 to 0: a2, a2, a0, a0.0213xmm2or m128aa0a0a2a2xmm1

Result singles 3 to 0: a2, a2, a0, a0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(4):
    j = i - i % 2
    xmm1.d[i] = src2.d[j]
# bits 128 and up of the register are unchanged

Run on AMD Zen 5 (EPYC 9645): 2 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.
OperandKindAction
MOVSLDUP xmm, xmm/m128
xmmexplicitwrite
xmm/m128explicitread

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms
SSE_TYPE_4

Attributes

What else XED records about the forms. How to read.

Memory forms
aligned memory operand

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to MOVSLDUP, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

IntrinsicCompiles to
_mm_moveldup_ps __m128 _mm_moveldup_ps(__m128 __a)

MOVSLDUP xmm, xmm Legacy -msse3

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.
ISA setCPUIDProcessors
SSE3

SSE3
CPUID.01H:ECX[0] SSE3

Every x86-64 processor in XED’s model and Zen 3 to Zen 6

More SSE3 instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, operands, flags, exception classes, attributes, ISA sets, CPUID bits and chip model.
  2. The CPU data of x86-64.net: Zen 3 to Zen 6, from GCC’s -march feature sets and AMD’s Processor Programming References, which the page of each processor cites.
  3. Clang's x86 intrinsic headers, LLVM 23.1.2 (commit 85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them.
  4. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026): Volume 2B, page 4-114 (MOVSLDUP)
  5. AMD64 Architecture Programmer's Manual, Volume 4: 128-Bit and 256-Bit Media Instructions (26568, rev. 3.25, November 2021), Wayback Machine copy of AMD's PDF

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang, part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.