MOVSS instruction (SSE)

MOVSS moves one single, the low 32 bits of an XMM register, and it is the oldest of the scalar moves, from the first SSE. It behaves as MOVSD does for doubles, whose page covers the three cases in full: a load from memory zeroes bits 127:32, a store writes four bytes, and a move between registers replaces bits 31:0 of the destination and keeps the other three singles. Zen 5’s recorded cases did each of these, and kept bits 511:128 of the destination as legacy SSE instructions do. The memory operand need not be aligned, and nothing is converted, so MXCSR plays no part. VMOVSS is the VEX and EVEX form.

One single, the rest zero

The register form’s merge is what makes one thing awkward: putting a single alone in a register, with zeros above it, as _mm_set_ss(x) asks for when x is already in a register. SSE has no MOVQ-like move for 32 bits within XMM registers, and in our builds at -O2 for the default target the two compilers work around that differently:

GCC 14 sends the value through a general-purpose register, movd eax, xmm0 and movd xmm0, eax (MOVD), which zero-extends on the way back.
Clang 23 zeroes another register with XORPS, merges the single into it with a register MOVSS, and copies the result back with MOVAPS.

With -march=x86-64-v2, which has SSE4.1, GCC clears the three upper singles with one INSERTPS with immediate 0Eh, and Clang blends with the zeroed register using BLENDPS with immediate 14 (1110b). Clang also replaces the merging move of _mm_move_ss, and a store to element 0 of a __m128, by BLENDPS with immediate 1, while GCC keeps MOVSS.

Loads and stores of float are MOVSS in both compilers; a copy between registers is MOVAPS, which writes the whole register, as Intel’s optimization guide recommends over a register MOVSS (Section 3.5.2.4).

In the optimization guide

What the optimization guide says about MOVSS, a line per claim. Each links to the claim in the guide, with its sources and where they differ.

Out of order

Partial register and flag writes: Scalar SSE instructions that write only the low element of an XMM register keep the rest of it, and so wait for its last writer: movss and movsd between registers, movlpd and movhpd from memory, and conversions and square roots such as cvtsi2sd and sqrtss.

Forms

Every encoding of MOVSS that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`MOVSS xmm, xmm` MOVSS_XMMss_XMMss_0F10	`F3 0F 10 /r`	SSE
`MOVSS xmm, xmm` MOVSS_XMMss_XMMss_0F11	`F3 0F 11 /r`	SSE
`MOVSS xmm, m32` MOVSS_XMMdq_MEMss	`F3 0F 10 /r`	SSE
`MOVSS m32, xmm` MOVSS_MEMss_XMMss	`F3 0F 11 /r`	SSE

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

The low single of xmm2 goes to the low end of xmm1; the others stay as they were.Register forms

Result singles 3 to 0: unchanged, unchanged, unchanged, a0.

The single in m32 goes to the low end of xmm1, and the rest of xmm1 is zeroed.MOVSS xmm, m32

Result singles 3 to 0: 0, 0, 0, a0.

The low single of xmm2 goes to m32.MOVSS m32, xmm

m32 receives single 0 of xmm2: a0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

xmm1.d[0] = xmm2.d[0]  # the others keep their values
# bits 128 and up of the register are unchanged

Run on AMD Zen 5 (EPYC 9645): 2 cases.

MOVSS xmm, m32

xmm1.write(mem.d[0])  # bits 127:32 zeroed
# bits 128 and up of the register are unchanged

Run on AMD Zen 5 (EPYC 9645): 1 case.

MOVSS m32, xmm

mem.d[0] = xmm2.d[0]

Run on AMD Zen 5 (EPYC 9645): 1 case.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`MOVSS xmm, xmm/m32`
`xmm`	explicit	write
`xmm/m32`	explicit	read
`MOVSS xmm/m32, xmm`
`xmm/m32`	explicit	write
`xmm`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms: SSE_TYPE_5

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to MOVSS, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`_mm_load_ss` `__m128 _mm_load_ss(const float *__p)`	`MOVSS xmm, m32` Legacy -msse
`_mm_move_ss` `__m128 _mm_move_ss(__m128 __a, __m128 __b)`	`MOVSS xmm, xmm` Legacy -msse
`_mm_store_ss` `void _mm_store_ss(float *__p, __m128 __a)`	`MOVSS m32, xmm` Legacy -msse

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`SSE` SSE	SSE `CPUID.01H:EDX[25]` SSE	Every x86-64 processor in XED’s model and Zen 3 to Zen 6

More SSE instructions

All 65 SSE instructions

One single, the rest zero#