MOVSX

MOVSX reads a signed byte or word and writes it to a wider register, filling the bits above it with copies of its sign bit. It is how compiled code loads signed char and short values: GCC 14 and Clang 23 at -O2 compile a read of *p, with p a short *, to movsx eax, word ptr [rdi] for an int result and to movsx rax, word ptr [rdi] for a long. MOVZX fills with zeros instead.

From 32 to 64 bits#

No MOVSX takes a 32-bit source. Widening an int to 64 bits is MOVSXD, which GCC and Clang both print as movsxd rax, edi; CDQE does the same for EAX alone in two bytes, and both compilers use it on an int that a call returned. The everyday case is an int array index: a[i] needs i sign-extended before it can enter a 64-bit address, where an unsigned index needs only a 32-bit MOV such as mov esi, esi.

Who extends a small argument#

For int f(short s) { return s; }, GCC emits movsx eax, di, while Clang emits a plain mov eax, edi and trusts the caller to have extended the argument; the System V page explains why that holds in practice but is not promised. Plain char is signed on x86-64 (sizes of C types), and both compilers treat it the same way.

Sizes#

• A 32-bit destination clears bits 63:32, so movsx eax, byte ptr [rdi] leaves a negative byte as a positive 64-bit value; a long result needs the 64-bit destination. A 16-bit destination keeps bits 63:16, like any 16-bit write.
• A word source with a 16-bit destination has nothing to extend: it copies the word.
• GNU’s AT&T syntax names both sizes, source first: movsbw, movsbl, movsbq, movswl, movswq, and movslq for MOVSXD.

Instead of a byte or word MOV#

A MOV into AL or AX merges the new bits with the rest of the register, so later readers wait for both; MOVSX into a 32- or 64-bit register replaces it whole. Intel’s optimization manual uses MOVSX that way to break such a dependency (Section 13.2.5). It also counts MOVSX among the register moves that Ivy Bridge cannot eliminate, where MOVZX from a low byte register qualifies (Example 3-21), and its Coding Rule 34 prefers zero extension where either will do.

Forms

Latency and throughput

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

dest.write(sext(src))            # from 8 or 16 bits to OSIZE: a 16-bit
                                 # register keeps bits 63:16, a 32-bit one
                                 # gets bits 63:32 cleared
# MOVSX r16, r/m16 has nothing to extend: it copies the word

Operands

Flags

None: XED records no flag that the forms test or change.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More General-purpose instructions

• INTO
• IRET
• Jcc
• JCXZ
• JECXZ
• JMP
• JRCXZ
• LDS
• LEA
• LEAVE
• LES
• LFS
• LGS
• LODS
• LOOP
• LOOPE
• LOOPNE
• LSS
• MOV
• MOVS
• MOVSXD
• MOVZX
• MUL
• NEG
• NOP
• NOT
• OR
• OUT
• OUTS
• PAUSE
• POP
• POPA
• POPF
• PUSH
• PUSHA
• PUSHF
• RCL
• RCR
• RET
• ROL

All 109 General-purpose instructions