x86-64.net

Instruction

MOVSXD

Sign-extends a 32-bit register or memory operand into a 64-bit register (AT&T movslq); 64-bit mode only, where it took over ARPL's opcode.

Extensions
Forms
3 (3 Legacy)
Data
Intel XED v2026.08.23

MOVSXD with REX.W reads a 32-bit register or memory operand and writes it to a 64-bit register, filling bits 63:32 with copies of bit 31. It is how 64-bit code widens an int: GCC 14 and Clang 23 at -O2 compile long f(int x) { return x; } to movsxd rax, edi, a load of *p from an int * into a long to movsxd rax, dword ptr [rdi], and (long)a * b to two MOVSXDs and a 64-bit IMUL. AT&T syntax calls it movslq. It changes no flag.

Indexes

The most frequent case is an int array index: a[i] with a long *a compiles to a MOVSXD of ESI and a load from [rdi + 8*rsi] (Clang extends into RAX), as an address needs all 64 bits of the index. When the int is already in EAX, as after a call, both compilers use the two-byte CDQE instead. Intel’s optimization manual loads two 32-bit indexes with one 64-bit MOV, extends the low one with MOVSXD and gets the high one with a SAR by 32 (Example 15-8).

Opcode 63

MOVSXD exists only in 64-bit mode: elsewhere, 63 is ARPL, a system instruction of protected mode, whose opcode 64-bit mode reused. The name is its own because MOVSX’s opcodes, 0F BE and 0F BF, take only byte and word sources.

Without REX.W

  • 32-bit operand size (63 /r alone) has nothing to extend: it is a 32-bit move, and like every 32-bit write it clears bits 63:32. Zen 5 turned a source of 80000000H into 0000000080000000H. Intel’s manual discourages this form in favour of MOV; AMD’s describes the result as zero-extended.
  • 16-bit operand size (66 63 /r) copies a word into a 16-bit register and keeps bits 63:16, by both manuals and on Zen 5.

The instruction table of AMD’s Zen 5 guide lists MOVSXD as one macro-op with a latency of 1, like MOV and MOVSX between registers.

Forms

Every encoding of MOVSXD that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
MOVSXD r16/32, m16/32 64-bit mode only MOVSXD_GPRz_MEMz63 /rLM
MOVSXD r64, m32 64-bit mode only MOVSXD_GPR64_MEMdREX.W 63 /rLM
MOVSXD r16/32/64, r16/32 64-bit mode only MOVSXD_GPRv_GPRz63 /rLM

Latency and throughput

What the scheduling models of LLVM 23.1.2 give for each form, not measurements: latency / reciprocal throughput in cycles, the ports under them. A row is a model, or models that agree; a dash, a form that its processors lack. Memory forms: latency from the address, ports without the load and store units. Which processors each model covers.
Modelr64, m32
Sandy Bridge, Haswell, Broadwell, Skylake, Skylake-SP, Ice Lake5 / 0.5p23
Alder Lake, Sapphire Rapids6 / 0.33p2 p3 p10
Lunar Lake6 / 0.33p20 p21 p22
Bonnell1 / 1p0
Silvermont3 / 1MEC
Piledriver5 / 1AGLU01 Load
Zen4 / 0.5AGU0 AGU1
Zen 24 / 0.33AGU0 AGU1 AGU2
Zen 3, Zen 45 / 0.33AGU0 AGU1 AGU2 LSU Load
Jaguar3 / 1LAGU

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

dest.write(sext(src))            # with REX.W, from 32 bits to 64; without,
                                 # nothing to extend: a 32-bit move clears
                                 # bits 63:32, a 16-bit one (66h) keeps
                                 # bits 63:16

Run on AMD Zen 5 (EPYC 9645): 45 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.
OperandKindAction
MOVSXD r16/32, m16/32 64-bit mode only MOVSXD r64, m32 64-bit mode only
r16/32/64explicitwrite
m16/32explicitread
MOVSXD r16/32/64, r16/32 64-bit mode only
r16/32/64explicitwrite
r16/32explicitread

Flags

None: XED records no flag that the forms test or change.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.
ISA setCPUIDProcessors
LONGMODE

LM
CPUID.80000001H:EDX[29] LM

Every x86-64 processor in XED’s model and Zen 3 to Zen 6

More General-purpose instructions

All 109 General-purpose instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, operands, flags, exception classes, attributes, ISA sets, CPUID bits and chip model.
  2. The CPU data of x86-64.net: Zen 3 to Zen 6, from GCC’s -march feature sets and AMD’s Processor Programming References, which the page of each processor cites.
  3. LLVM 23.1.2's x86 scheduling models (commit 85ac56026243): the latency, reciprocal throughput and ports of each form, as llvm-mca reports them.
  4. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026): Volume 2B, page 4-120 (MOVSX/MOVSXD)
  5. AMD64 Architecture Programmer's Manual, Volume 3: General-Purpose and System Instructions (24594, rev. 3.39, October 2026)
  6. Intel 64 and IA-32 Architectures Optimization Reference Manual, Volume 1 (248966-051, October 2026)
  7. Software Optimization Guide for the AMD Zen5 Microarchitecture (58455, rev. 1.00, August 2024), Wayback Machine copy of AMD's ZIP

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The timings come from LLVM's scheduling models, part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.