x86-64.net

Instruction

MOVSXD

Sign-extends a 32-bit register or memory operand into a 64-bit register (AT&T movslq); 64-bit mode only, where it took over ARPL's opcode.

Extensions
Forms
3 (3 Legacy)
Data
Intel XED v2026.08.23

Forms

Every encoding of MOVSXD that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
MOVSXD r32, m32 64-bit mode only MOVSXD_GPRz_MEMz63 /rLM
MOVSXD r64, m32 64-bit mode only MOVSXD_GPR64_MEMdREX.W 63 /rLM
MOVSXD r32, r32 64-bit mode only MOVSXD_GPRv_GPRz63 /rLM

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, which covers AMD processors up to Zen 2.
ISA setCPUIDProcessors in XED
LONGMODE

LM
CPUID.80000001H:EDX[29] LM

Every x86-64 processor in XED’s model

More General-purpose instructions

All 109 General-purpose instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model.
  2. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-092, June 2026)
  3. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The text is our own.