MOVUPD instruction (SSE2)

MOVUPD copies 16 bytes between XMM registers, or between an XMM register and memory at any address, read as two doubles but not interpreted. It is MOVUPS with a 66 prefix, which came with SSE2, and that page covers what the two share: no alignment fault, bits 128 and up of the register kept on a load (see mixing SSE and AVX), the two register encodings and the cost of crossing a cache line. VMOVUPD is the VEX and EVEX form, with masks by double, and MOVAPD the aligned move. On Zen 5, the four recorded cases cover the load, the store and both register encodings, 66 0F 10 and 66 0F 11.

Which name the compilers write

The extra byte changes nothing in what is moved, so the choice is the compiler’s. In our builds at -O2, with the default target and with -march=x86-64-v2:

A loop such as d[i] = s[i] * 2.0 over restrict pointers to double loads with MOVUPD in GCC 14 and Clang 23. GCC stores the result with MOVUPS, Clang with MOVUPD.
_mm_loadu_pd is MOVUPD in GCC and MOVUPS in Clang, and _mm_storeu_pd is MOVUPS in both.
Between registers, the compilers copy doubles with MOVAPD or MOVAPS, not with MOVUPD, although Intel’s optimization manual lists the MOVUPD register form, like MOVAPD’s, among the moves that Ivy Bridge executes without latency (Section 3.5.1.12).

Since legacy SSE arithmetic such as ADDPD needs its memory operand aligned to 16 bytes, a load whose address is not known to be aligned stays a separate MOVUPD in front of it, as in the loop above. AMD’s latency spreadsheet for Zen 5 gives MOVUPD, like MOVUPS, one macro-op and four per cycle, and its guide says that on aligned data the aligned and unaligned moves perform the same (Section 2.6.2).

In the optimization guide

What the optimization guide says about MOVUPD, a line per claim. Each links to the claim in the guide, with its sources and where they differ.

Redwood Cove

Front end: Redwood Cove fuses a load into a register with the operation on that register that follows it.
Front end: Redwood Cove’s load-and-operate fusion takes only some loads, addresses and operations.

Silvermont to Goldmont Plus

Loads, stores and caches: Unaligned vector loads are one micro-op, but line splits are slow; Intel suggests aligned loads and palignr.

Forms

Every encoding of MOVUPD that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`MOVUPD xmm, m128` MOVUPD_XMMpd_MEMpd	`66 0F 10 /r`	SSE2
`MOVUPD xmm, xmm` MOVUPD_XMMpd_XMMpd_0F10	`66 0F 10 /r`	SSE2
`MOVUPD m128, xmm` MOVUPD_MEMpd_XMMpd	`66 0F 11 /r`	SSE2
`MOVUPD xmm, xmm` MOVUPD_XMMpd_XMMpd_0F11	`66 0F 11 /r`	SSE2

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

A move: each double is copied to the same place.

The store forms copy the same way, from the register to memory.

Result double i is double i of xmm2. Result doubles 1 to 0: a1, a0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

dest.write(src2.read())
# a register destination: bits 128 and up are unchanged

Run on AMD Zen 5 (EPYC 9645): 4 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`MOVUPD xmm, xmm/m128`
`xmm`	explicit	write
`xmm/m128`	explicit	read
`MOVUPD xmm/m128, xmm`
`xmm/m128`	explicit	write
`xmm`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms: SSE_TYPE_4M

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to MOVUPD, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`_mm_loadu_pd` `__m128d _mm_loadu_pd(const double *__dp)`	`MOVUPD xmm, m128` Legacy -msse2
`_mm_storeu_pd` `void _mm_storeu_pd(double *__dp, __m128d __a)`	`MOVUPD m128, xmm` Legacy -msse2

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`SSE2` SSE2	SSE2 `CPUID.01H:EDX[26]` SSE2	Every x86-64 processor in XED’s model and Zen 3 to Zen 6

More SSE2 instructions

All 124 SSE2 instructions

Which name the compilers write#