MOVUPS instruction (SSE)

MOVUPS copies 16 bytes between XMM registers, or between an XMM register and memory at any address. It came with the first SSE and needs no prefix, which makes it the shortest unaligned 16-byte load and store, and since it does not look at the bits, compilers use it for data of every type. VMOVUPS is the VEX and EVEX form, with masks and wider registers; MOVAPS is the same move for aligned addresses, and MOVDQU and MOVUPD the same bits under integer and double names.

What the legacy form keeps

A load writes bits 127:0 and leaves the rest of the register as it was: on Zen 5, the recorded movups xmm4, xmmword ptr [mem] replaced the low 16 bytes of ZMM4 and kept the other 48 (see mixing SSE and AVX). Like MOVAPS, it has two register encodings, 0F 10 writing ModRM.reg and 0F 11 writing ModRM.rm, and Zen 5 ran both. In our builds, compilers copy registers with MOVAPS instead, of the same length; Intel’s optimization manual lists either between XMM registers as a move that Ivy Bridge executes without latency (Section 3.5.1.12).

In baseline code

In our builds at -O2, with the default target and with -march=x86-64-v2:

A loop such as d[i] = s[i] * 2.0f over restrict pointers loads and stores with MOVUPS in GCC 14 and Clang 23. Legacy SSE arithmetic needs its memory operand aligned, so the load stays a separate instruction.
A 16- or 32-byte memcpy and the copy of a 16-byte struct are MOVUPS loads and stores in Clang; GCC loads with MOVDQU and stores with MOVUPS.
Clang compiles _mm_loadu_si128 and _mm_loadu_pd to MOVUPS, and both compilers store doubles from _mm_storeu_pd with it.

The U removes the fault, not the cost of crossing a line: AMD’s Zen 5 guide gives the two moves the same speed on aligned data and half the throughput for an access that spans a 64-byte boundary (Section 2.6.2). With alignment checking on, the manuals differ on when a misaligned MOVUPS raises #AC, as MOVDQU explains.

In the optimization guide

What the optimization guide says about MOVUPS, a line per claim. Each links to the claim in the guide, with its sources and where they differ.

Memory

Cache lines, alignment and splits: In a stream of consecutive accesses that all start at the same misalignment, the share that splits a line grows with the width: one 16-byte access in four, every second 32-byte AVX access and every 64-byte AVX-512 access.

Redwood Cove

Front end: Redwood Cove fuses a load into a register with the operation on that register that follows it.
Front end: Redwood Cove’s load-and-operate fusion takes only some loads, addresses and operations.

Silvermont to Goldmont Plus

Out-of-order and in-order execution: Goldmont eliminates register-to-register moves of XMM registers; Silvermont does not. sources differ
Loads, stores and caches: Unaligned vector loads are one micro-op, but line splits are slow; Intel suggests aligned loads and palignr.

Forms

Every encoding of MOVUPS that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`MOVUPS xmm, m128` MOVUPS_XMMps_MEMps	`NP 0F 10 /r`	SSE
`MOVUPS xmm, xmm` MOVUPS_XMMps_XMMps_0F10	`NP 0F 10 /r`	SSE
`MOVUPS m128, xmm` MOVUPS_MEMps_XMMps	`NP 0F 11 /r`	SSE
`MOVUPS xmm, xmm` MOVUPS_XMMps_XMMps_0F11	`NP 0F 11 /r`	SSE

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

A move: each single is copied to the same place.

The store forms copy the same way, from the register to memory.

Result single i is single i of xmm2. Result singles 3 to 0: a3, a2, a1, a0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

dest.write(src2.read())
# a register destination: bits 128 and up are unchanged

Run on AMD Zen 5 (EPYC 9645): 4 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`MOVUPS xmm, xmm/m128`
`xmm`	explicit	write
`xmm/m128`	explicit	read
`MOVUPS xmm/m128, xmm`
`xmm/m128`	explicit	write
`xmm`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms: SSE_TYPE_4M

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to MOVUPS, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`_mm_loadu_ps` `__m128 _mm_loadu_ps(const float *__p)`	`MOVUPS xmm, m128` Legacy -msse
`_mm_storeu_ps` `void _mm_storeu_ps(float *__p, __m128 __a)`	`MOVUPS m128, xmm` Legacy -msse
`_mm_storeu_si128` `void _mm_storeu_si128(__m128i_u *__p, __m128i __b)`	`MOVUPS m128, xmm` Legacy -msse2

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`SSE` SSE	SSE `CPUID.01H:EDX[25]` SSE	Every x86-64 processor in XED’s model and Zen 3 to Zen 6

More SSE instructions

All 65 SSE instructions

What the legacy form keeps#

In baseline code#