x86-64.net

Instruction

MOVZX

Copies an unsigned byte or word into a wider register, filling the upper bits with zeros.

Extensions
Forms
7 (7 Legacy)
Data
Intel XED v2026.08.23

Forms

Every encoding of MOVZX that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
MOVZX r16/32/64, m8 MOVZX_GPRv_MEMb0F B6 /rBase instruction set
MOVZX r16/32/64, m16 not in 64-bit mode MOVZX_GPRv_MEMw0F B7 /rBase instruction set
MOVZX r64, m16 64-bit mode only MOVZX_GPR64_MEMwREX.W 0F B7 /rBase instruction set
MOVZX r16, m16 64-bit mode only MOVZX_GPR16_MEMw66 0F B7 /rBase instruction set
MOVZX r32, m16 64-bit mode only MOVZX_GPR32_MEMw0F B7 /rBase instruction set
MOVZX r16/32/64, r8 MOVZX_GPRv_GPR80F B6 /rBase instruction set
MOVZX r16/32/64, r16 MOVZX_GPRv_GPR160F B7 /rBase instruction set

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to MOVZX, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

IntrinsicCompiles to
_load_mask16 __mmask16 _load_mask16(__mmask16 *__A)

MOVZX r32, m16 Legacy -mavx512f

_load_mask8 __mmask8 _load_mask8(__mmask8 *__A)

MOVZX r16/32/64, m8 Legacy -mavx512dq

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, which covers AMD processors up to Zen 2.
ISA setCPUIDProcessors in XED
I386

No CPUID bit: part of the base instruction set.

Every x86-64 processor in XED’s model

More General-purpose instructions

All 109 General-purpose instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model.
  2. Clang's x86 intrinsic headers, LLVM 23.1.2 (commit 85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them.
  3. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-092, June 2026)
  4. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang, part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.