MUL

MUL is the unsigned multiplication, and it has a single shape: rAX times the operand, with the whole product, twice as wide, in rDX:rAX (in AX for bytes, AH holding the upper half). RDX is written even when the upper half is 0, and no form takes an immediate or another destination.

The upper half#

MUL exists for the upper half. When only the lower one is needed, compilers use the two-operand IMUL, whose low bits are the same for unsigned numbers and which names its registers freely: GCC 14 and Clang 23 at -O2 compile a * b on uint64_t to imul rax, rsi. A 32-bit by 32-bit product needs no MUL either, since both factors fit in 64-bit registers: (uint64_t)a * b with 32-bit a and b becomes two zero-extending MOVs and a 64-bit IMUL.

The upper half of a 64-bit product is where MUL appears:

• (unsigned __int128)a * b becomes a MOV of one factor into RAX and a MUL by the other, which leaves the product exactly where the System V ABI returns an __int128, in RDX:RAX; ((unsigned __int128)a * b) >> 64 adds mov rax, rdx.
• Unsigned division of a 64-bit value by a constant keeps the upper half of a product with a scaled reciprocal: x / 10 becomes a MOVABS of 0xCCCCCCCCCCCCCCCD, a MUL, and a right shift of the upper half by 3 (see DIV).
• __builtin_mul_overflow on two uint64_ts is MUL followed by seto al: MUL sets CF and OF together when the upper half is not 0, that is when the product does not fit in 64 bits.

MULX#

MULX from BMI2 is MUL with free choice of its two destination registers, one source still fixed in RDX, and no flags written. With -mbmi2, GCC uses it for the 128-bit product and Clang also for the upper half alone and the division by a constant; an overflow check still needs MUL, for its flags.

On Zen 5, AMD’s guide gives a 64-bit by 64-bit multiplication a latency of 3 cycles, fully pipelined, and one cycle more for the second result of an instruction with two destination registers, such as MUL (Section 2.10.2).

In the optimization guide

What the optimization guide says about MUL, a line per claim. Each links to the claim in the guide, with its sources and where they differ.

Bulldozer to Excavator

• Integer execution: EX1’s pipelined multiplier takes 4 cycles for operands of up to 32 bits, starting one every 2 cycles, and 6 for 64-bit operands, starting one every 4; LLVM’s model agrees.

Golden Cove and Raptor Cove

• Integer execution: A MUL of 64 by 64 bits into RDX:RAX is two micro-ops: the low half on port 1 and the high half on port 5, four cycles in LLVM’s models against three for an IMUL that keeps only the low half.

Jaguar and Puma

• Integer execution: The pipelined multiplier takes 3 cycles for operands of up to 32 bits, one a cycle, and 6 for 64-bit ones, one every 4; a form that writes two registers, such as MUL, adds a cycle to both. sources differ

Sandy Bridge and Ivy Bridge

• Integer and vector execution: Separate multipliers serve general-purpose and vector registers: a general-purpose multiply runs on port 1 at a latency of 3 cycles, a vector one on port 0 at 5 cycles for any precision, and both run one operation a cycle.

Silvermont to Goldmont Plus

• Out-of-order and in-order execution: On Silvermont the widening one-operand mul and imul come from microcode; use the two-operand imul where the high half is not needed.

Skylake to Cooper Lake

• Integer execution: A MUL of 64 by 64 bits into RDX:RAX is two micro-ops on ports 1 and 5 and takes four cycles in LLVM’s models, against three for an IMUL that keeps only the low half.

Zen and Zen+

• Integer execution: One ALU multiplies, up to 64 by 64 bits in three cycles, pipelined; a multiplication with two destination registers delivers the second a cycle later and starts only every other cycle. sources differ

Zen 2

• Integer execution: One ALU multiplies, 64 by 64 bits in three cycles and pipelined; a multiplication that writes two registers delivers the second a cycle later and starts only every other cycle.

Zen 3

• Integer execution: Only ALU 1 multiplies, 64 by 64 bits in three cycles and pipelined; a multiplication that writes two registers delivers the second one a cycle later.

Zen 4

• Integer execution: Only one ALU multiplies, 64 by 64 bits in three cycles and pipelined; a multiplication that writes two registers delivers the second one a cycle later.

Zen 5

• Integer execution: Three ALUs multiply, 64 by 64 bits in three cycles; a multiplication that writes two registers delivers the second one a cycle later.

Forms

Latency and throughput

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

p = rAX * src                    # AL, AX, EAX or RAX times the source: a
                                 # product of 2 * OSIZE bits
if OSIZE == 8:
    ax = p                       # AH:AL
else:                            # EDX and EAX: bits 63:32 cleared
    rDX = p >> OSIZE             # the high half
    rAX = p                      # the low half
if not nf:                       # NF=1 (APX) leaves the flags as they were
    cf = of = p >> OSIZE != 0    # the high half is not zero
    sf = zf = af = pf = UNDEFINED

Operands

Flags

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

Legacy forms

none in XED

EVEX forms

APX-EVEX-INT

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More General-purpose instructions

• JCXZ
• JECXZ
• JMP
• JRCXZ
• LDS
• LEA
• LEAVE
• LES
• LFS
• LGS
• LODS
• LOOP
• LOOPE
• LOOPNE
• LSS
• MOV
• MOVS
• MOVSX
• MOVSXD
• MOVZX
• NEG
• NOP
• NOT
• OR
• OUT
• OUTS
• PAUSE
• POP
• POPA
• POPF
• PUSH
• PUSHA
• PUSHF
• RCL
• RCR
• RET
• ROL
• ROR
• SALC
• SAR

All 109 General-purpose instructions

More APX instructions

• DIV
• ENQCMD
• ENQCMDS
• IDIV
• IMUL
• INC
• INVEPT
• INVPCID
• INVVPID
• JMPABS
• KMOVB
• KMOVD
• KMOVQ
• KMOVW
• LDTILECFG
• LZCNT
• MOVBE
• MOVDIR64B
• MOVDIRI
• MOVRS
• MULX
• NEG
• NOT
• OR
• PDEP
• PEXT
• POP2
• POP2P
• POPCNT
• POPP
• PUSH2
• PUSH2P
• PUSHP
• RCL
• RCR
• RDMSR
• ROL
• ROR
• RORX
• SAR

All 88 APX instructions