MULPD instruction (SSE2)

MULPD multiplies two pairs of doubles, each product rounded once as MXCSR says. VMULPD is the VEX and EVEX form, and its page shows the rounding modes at work and why a division by a power of two compiles to a multiplication; MULPS covers MXCSR, FTZ and DAZ. This SSE2 encoding belongs to every x86-64 processor. It writes the product over its first operand, keeps bits 128 and up of the register (see SSE and AVX) and needs a memory operand aligned to 16 bytes, or it raises #GP.

Signs and signaling NaNs on Zen 5

A product of zeros takes the exclusive OR of their signs, whatever the rounding. In Zen 5’s recorded cases, -0 times -0 gave +0 both rounding up and rounding toward zero, and -0 times +0 gave -0; infinity times infinity gave infinity and set no flag.

With MXCSR’s IM bit clear, a signaling NaN makes the instruction fault instead. mulpd xmm0, xmm13 under MXCSR 1F00H, with a signaling NaN times 1 below and 1 times a quiet NaN above, raised #XM, set IE and left XMM0 exactly as it was, the upper double included, although a quiet NaN alone raises nothing. With every exception unmasked, MXCSR 0, a case with signaling NaNs in both elements did the same.

Products without their sum

In our builds at -O2 for the default target, GCC 14 and Clang 23 compile a[i] = b[i] * c[i] over global arrays of doubles to MULPD with c read from memory, and b[i] * s after broadcasting s with UNPCKLPD. A dot product, t += b[i] * c[i], is another matter. GCC multiplies two elements at a time but still adds the products to t one by one, with ADDSD, UNPCKHPD and ADDSD, as reordering the additions would change the rounded sum; Clang keeps the whole loop scalar.

AMD’s latency spreadsheet for Zen 5 lists MULPD like VMULPD: one macro-op on pipes FP0 and FP1, a latency of 3 cycles and two per cycle.

In the optimization guide

What the optimization guide says about MULPD, a line per claim. Each links to the claim in the guide, with its sources and where they differ.

Haswell and Broadwell

What Broadwell changed: Broadwell cuts the latency of floating-point multiplication from 5 cycles to 3, for SSE and AVX code and, by Intel’s manual, x87 as well; FMA stays at 5. sources differ

Silvermont to Goldmont Plus

Vectors and cryptography: Packed adds and multiplies are slower than scalar on Silvermont, mulpd most of all; Goldmont runs them one a cycle.

Forms

Every encoding of MULPD that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`MULPD xmm, m128` MULPD_XMMpd_MEMpd	`66 0F 59 /r`	SSE2
`MULPD xmm, xmm` MULPD_XMMpd_XMMpd	`66 0F 59 /r`	SSE2

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Element-wise: each double of the result comes from the double in the same place in each source.

Result double i comes from double i of xmm1 and xmm2. Result doubles 1 to 0: a1×b1, a0×b0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(2):
    a = xmm1.f64[i]
    b = src2.f64[i]
    xmm1.f64[i] = mul(a, b)
# bits 128 and up of the register are unchanged

Run on AMD Zen 5 (EPYC 9645): 9 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`MULPD xmm, xmm/m128`
`xmm`	explicit	read, write
`xmm/m128`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms: SSE_TYPE_2

Attributes

What else XED records about the forms. How to read.

All forms: follows MXCSR
Memory forms: aligned memory operand

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to MULPD, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`_mm_mul_pd` `__m128d _mm_mul_pd(__m128d __a, __m128d __b)`	`MULPD xmm, xmm` Legacy -msse2

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`SSE2` SSE2	SSE2 `CPUID.01H:EDX[26]` SSE2	Every x86-64 processor in XED’s model and Zen 3 to Zen 6

More SSE2 instructions

All 124 SSE2 instructions

Signs and signaling NaNs on Zen 5#

Products without their sum#