MULPS instruction (SSE)

MULPS multiplies four pairs of singles and rounds each product once; MULSS multiplies the lowest pair. Where a cheaper instruction gives the same bits, compilers use it: GCC 14 and Clang 23 at -O2 compile x * 2.0f to addss xmm0, xmm0.

MXCSR

Every SSE and AVX floating-point instruction takes its settings from MXCSR and reports to it:

bits 14:13 choose the rounding: to nearest even (00), down (01), up (10) or toward zero (11);
bits 5:0 are the flags of the six exceptions (invalid operation, denormal operand, divide by zero, overflow, underflow, precision), which stay set until software clears them;
bits 12:7 mask them: a masked exception gives its default result and sets its flag, an unmasked one raises #XM;
bits 15 and 6 are FTZ and DAZ, below.

A process starts with 1F80H: round to nearest, every exception masked. C’s fesetround changes the rounding bits, and the System V ABI asks each function to leave the control bits as it found them (see registers). Intel’s optimization guide notes that reading MXCSR is slow and writing it serializes the processor, and advises against changing it often (Sections 3.9.3 and 7.5.2).

Denormals, FTZ and DAZ

Products of small numbers underflow easily, and denormals cost time. AMD’s guide for Zen 5 names multiply, divide and square root among the operations that may run again, at a longer latency, when they meet a denormal input or result, unless FTZ and DAZ are set (Section 2.11.2); Intel’s says that an FP32 or FP64 operation on a denormal may be handed to a slower routine (Section 18.5.4). The two bits trade IEEE 754 conformance for speed:

FTZ turns a result that would be denormal into a zero of the same sign, setting the underflow and precision flags, as long as underflow is masked.
DAZ reads denormal inputs as zeros of the same sign and no longer reports the denormal-operand exception.

Both guides recommend setting both where denormal precision does not matter. GCC 14 and Clang 23 link crtfastmath.o into a program built with -ffast-math, -Ofast or -funsafe-math-optimizations, though not into a shared library, and it sets both at startup: the test program built that way with GCC read MXCSR as 9FC0H. That affects every library the program calls. The x87 unit has no such bits, as AMD’s guide points out (Section 2.11.4).

In the optimization guide

What the optimization guide says about MULPS, a line per claim. Each links to the claim in the guide, with its sources and where they differ.

Haswell and Broadwell

What Broadwell changed: Broadwell cuts the latency of floating-point multiplication from 5 cycles to 3, for SSE and AVX code and, by Intel’s manual, x87 as well; FMA stays at 5. sources differ

Silvermont to Goldmont Plus

Out-of-order and in-order execution: On Silvermont, put the stores of an unrolled multiply-add loop at its end, so that they do not block the next multiply.
Vectors and cryptography: Packed adds and multiplies are slower than scalar on Silvermont, mulpd most of all; Goldmont runs them one a cycle.

Forms

Every encoding of MULPS that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`MULPS xmm, m128` MULPS_XMMps_MEMps	`NP 0F 59 /r`	SSE
`MULPS xmm, xmm` MULPS_XMMps_XMMps	`NP 0F 59 /r`	SSE

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Element-wise: each single of the result comes from the single in the same place in each source.

Result single i comes from single i of xmm1 and xmm2. Result singles 3 to 0: a3×b3, a2×b2, a1×b1, a0×b0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(4):
    a = xmm1.f32[i]
    b = src2.f32[i]
    xmm1.f32[i] = mul(a, b)
# bits 128 and up of the register are unchanged

Run on AMD Zen 5 (EPYC 9645): 2 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`MULPS xmm, xmm/m128`
`xmm`	explicit	read, write
`xmm/m128`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms: SSE_TYPE_2

Attributes

What else XED records about the forms. How to read.

All forms: follows MXCSR
Memory forms: aligned memory operand

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to MULPS, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`_mm_mul_ps` `__m128 _mm_mul_ps(__m128 __a, __m128 __b)`	`MULPS xmm, xmm` Legacy -msse

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`SSE` SSE	SSE `CPUID.01H:EDX[25]` SSE	Every x86-64 processor in XED’s model and Zen 3 to Zen 6

More SSE instructions

All 65 SSE instructions

MXCSR#

Denormals, FTZ and DAZ#