MULSD instruction (SSE2)

MULSD multiplies the low double of its destination by the low double of its source and keeps the high double. It is SSE2’s scalar form of MULPD; MULSS shows how constants and pow compile, and ADDSS covers what the scalar forms share. GCC 14 and Clang 23 at -O2 compile a * b over double to mulsd xmm0, xmm1, x * x * x to two MULSD, and a product over a global array, p *= da[i], to a chain of MULSD reading memory, in the order of the source. In Zen 5’s two recorded cases:

With MXCSR at FFC0H (round toward zero, FTZ and DAZ set), the largest denormal times the smallest normal double, from memory, gave +0 and set no flag: DAZ reads the denormal as zero, and no denormal operand is reported.
Under 1F80H, the signaling NaN 7FF0000000012345H times the quiet NaN 7FF8000000012345H gave 7FF8000000012345H, the first operand quieted, and set IE.

Polynomials and FMA

The x86-64 baseline has no fused multiply-add, so Horner’s rule, ((2.0 * x + 3.0) * x + 4.0) * x + 5.0, is a chain of MULSD and ADDSD in our builds, each rounding once: both compilers compute 2.0 * x as x + x and take the constants from memory. With -march=x86-64-v3 the same code becomes three VFMADD213SD, since both compilers contract a multiplication and an addition in one expression by default. Each FMA rounds once instead of twice, so the result can differ in the last bit from the baseline build.

AMD’s latency spreadsheet for Zen 5 lists MULSD at 3 cycles on pipes FP0 and FP1, and its guide recommends an FMA where a multiplication feeds an addition on the critical path (Section 2.11.7). The legacy form keeps bits 255:128 (see mixing SSE and AVX); VMULSD is the VEX and EVEX form.

Forms

Every encoding of MULSD that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`MULSD xmm, m64` MULSD_XMMsd_MEMsd	`F2 0F 59 /r`	SSE2
`MULSD xmm, xmm` MULSD_XMMsd_XMMsd	`F2 0F 59 /r`	SSE2

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Scalar: only the low double is computed; the other double comes from xmm1.

Result double 0 is computed from double 0 of xmm1 and xmm2; double 1 is that of xmm1. Result doubles 1 to 0: a1, a0×b0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

xmm1.f64[0] = mul(xmm1.f64[0], src2.f64[0])
# xmm1.q[1] keeps its value
# bits 128 and up of the register are unchanged

Run on AMD Zen 5 (EPYC 9645): 2 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`MULSD xmm, xmm/m64`
`xmm`	explicit	read, write
`xmm/m64`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms: SSE_TYPE_3

Attributes

What else XED records about the forms. How to read.

All forms: follows MXCSR

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to MULSD, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`_mm_mul_sd` `__m128d _mm_mul_sd(__m128d __a, __m128d __b)`	`MULSD xmm, xmm` Legacy -msse2

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`SSE2` SSE2	SSE2 `CPUID.01H:EDX[26]` SSE2	Every x86-64 processor in XED’s model and Zen 3 to Zen 6

More SSE2 instructions

All 124 SSE2 instructions

Polynomials and FMA#