MULSS instruction (SSE)

MULSS multiplies the low single of its destination by the low single of its source and keeps singles 1 to 3 of the destination. It is the scalar form of MULPS, whose page covers MXCSR, FTZ and DAZ; ADDSS covers what the scalar forms share, from the kept elements to the memory operand of four bytes at any alignment. GCC 14 and Clang 23 at -O2 compile a * b over float to mulss xmm0, xmm1.

Constants of the other type

A floating constant without a suffix is a double, so f * 0.1 with a float f is computed in double precision: in our builds both compilers convert f with CVTSS2SD, multiply with MULSD and convert back with CVTSD2SS. For f * 3.0 they emit one MULSS by 3.0f instead: the double product of a single and 3 is exact, so rounding it to a single gives the same bits as MULSS. Other constants take other routes in both compilers:

f * 2.0f is addss xmm0, xmm0, and f * -1.0f an XORPS that flips the sign;
powf(f, 2.0f) is mulss xmm0, xmm0 in GCC, while Clang calls powf unless -fno-math-errno is given.

Small products on Zen 5

Under MXCSR’s default, 1F80H, mulss xmm4, xmm4 squared the denormal -2^-127 to +0, the exact product 2^-254 being far below the smallest denormal, and set UE, PE and DE. AMD’s guide for Zen 5 names multiplication among the operations that may run again at a longer latency on such inputs unless FTZ and DAZ are set (Section 2.11.2). With MXCSR at FFC0H, two quiet NaNs, 7FC00000H in the register times FFC00000H from memory, gave the register’s NaN and set no flag.

AMD’s latency spreadsheet for Zen 5 lists it at 3 cycles on pipes FP0 and FP1. The legacy form keeps bits 255:128 (see mixing SSE and AVX); VMULSS is the VEX and EVEX form.

Forms

Every encoding of MULSS that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`MULSS xmm, m32` MULSS_XMMss_MEMss	`F3 0F 59 /r`	SSE
`MULSS xmm, xmm` MULSS_XMMss_XMMss	`F3 0F 59 /r`	SSE

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Scalar: only the low single is computed; the other singles come from xmm1.

Result single 0 is computed from single 0 of xmm1 and xmm2; singles 3 to 1 are those of xmm1. Result singles 3 to 0: a3, a2, a1, a0×b0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

xmm1.f32[0] = mul(xmm1.f32[0], src2.f32[0])
# xmm1.d[1] to [3] keep their values
# bits 128 and up of the register are unchanged

Run on AMD Zen 5 (EPYC 9645): 2 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`MULSS xmm, xmm/m32`
`xmm`	explicit	read, write
`xmm/m32`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms: SSE_TYPE_3

Attributes

What else XED records about the forms. How to read.

All forms: follows MXCSR

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to MULSS, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`_mm_mul_ss` `__m128 _mm_mul_ss(__m128 __a, __m128 __b)`	`MULSS xmm, xmm` Legacy -msse

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`SSE` SSE	SSE `CPUID.01H:EDX[25]` SSE	Every x86-64 processor in XED’s model and Zen 3 to Zen 6

More SSE instructions

All 65 SSE instructions

Constants of the other type#

Small products on Zen 5#