MULX

MULX multiplies RDX, or EDX for 32 bits, by its source, unsigned, and writes the double-width product to two registers of its choice without touching the flags. In Intel syntax the register for the high half comes first: mulx r9, r8, rsi puts the upper 64 bits of RDX * RSI in R9 and the lower 64 bits in R8. MUL instead takes its other factor from RAX, always writes RDX:RAX and sets CF and OF.

Why no flags#

Multiplying integers of several words adds partial products in carry chains, and the flags MUL writes would break a chain of ADC between two steps. MULX leaves CF and OF alone, so its products can be interleaved with ADC, or with ADCX and ADOX, which carry through CF and OF only and so run two chains at once. Intel’s optimization manual shows such a carry chain and says that MULX can speed up computations on large integers, such as RSA’s, significantly (Section 14.5.1.1). The free choice of destinations also saves the moves that MUL’s fixed registers need.

One register for both halves#

If both destinations name the same register, it ends up holding the high half, as the page’s pseudocode writes it last; Zen 5 did so in every recorded case. Clang 23 uses this: with -march=x86-64-v3 at -O2 it compiles the high half of a 64-bit product, (unsigned __int128)a * b >> 64, to mulx rax, rax, rdi, and does the same for the multiplication by a reciprocal that replaces x / 10. GCC 14 keeps MUL for both, and uses MULX for the full 128-bit product. The intrinsic _mulx_u64(a, b, &hi) returns the low half and stores the high one; both compilers emit MULX and a store.

Speed#

The instruction table of AMD’s Zen 5 guide lists MULX as two macro-ops with a latency of four cycles, on the multiplier that three of Zen 5’s integer ALUs have (Section 2.10.2). Intel’s optimization manual places it, with MUL and IMUL, on the single “slow integer” unit of Golden Cove (Table 2-4).

MULX belongs to BMI2, part of x86-64-v3; APX adds an EVEX form that reaches its new registers.

Forms

Latency and throughput

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

p = rDX * src                    # EDX or RDX times the source, unsigned: a
                                 # product of 2 * OSIZE bits
lo.write(p)                      # the low half, then the high half: when
hi.write(p >> OSIZE)             # hi and lo are one register, the high
                                 # half is what stays
# no flag changes

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

VEX forms

none in XED

EVEX forms

APX-EVEX-BMI

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to MULX, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More BMI2 instructions

• BZHI
• PDEP
• PEXT
• RORX
• SARX
• SHLX
• SHRX

More APX instructions

• ENQCMD
• ENQCMDS
• IDIV
• IMUL
• INC
• INVEPT
• INVPCID
• INVVPID
• JMPABS
• KMOVB
• KMOVD
• KMOVQ
• KMOVW
• LDTILECFG
• LZCNT
• MOVBE
• MOVDIR64B
• MOVDIRI
• MOVRS
• MUL
• NEG
• NOT
• OR
• PDEP
• PEXT
• POP2
• POP2P
• POPCNT
• POPP
• PUSH2
• PUSH2P
• PUSHP
• RCL
• RCR
• RDMSR
• ROL
• ROR
• RORX
• SAR
• SARX

All 88 APX instructions