MWAIT

MWAIT lets the core stop once MONITOR has armed the address monitor, until a store hits the watched range or an interrupt or another event arrives. It changes no register and no flag, so the program cannot tell why it woke and must look at its flag again. If the monitor is not armed, or a store has already triggered it, MWAIT does not wait at all; either way the monitor is clear afterwards, and the next wait needs a new MONITOR. This is how operating systems idle a processor: another processor wakes it by writing a word, without an interrupt between processors.

The hint in EAX#

Bits 7:4 of EAX name the target C-state minus one (0 for C1, 0FH for C0) and bits 3:0 a sub-state of it; CPUID leaf 05H lists the sub-states, and the processor may choose another state. The depth matters for who can wake it: Intel’s manual warns that beyond C1 a store from a device rather than a processor may not end the wait, and AMD’s manual names only stores from another processor.

Extensions in ECX#

• Bit 0 makes an interrupt end the wait even with IF clear (CPUID leaf 05H, ECX bit 1), so an idle loop can check for work with interrupts off and sleep; the interrupt that wakes it is delivered once the kernel sets IF again.
• Bit 2, in Intel’s manual only, is monitorless MWAIT (leaf 05H, ECX bit 3): it waits whether or not a monitor is armed, ignoring stores, until an interrupt or another event. Intel also enumerates processors with MWAIT but no MONITOR (leaf 07H, sub-leaf 1, EDX bit 23), where this bit must be set.

Other ECX bits raise #GP; AMD’s manual defines bit 0 alone.

Privilege#

As with MONITOR, Intel allows MWAIT only at CPL 0 (#UD elsewhere), and AMD at CPL 3 too when the operating system sets MonMwaitUserEn in MSR C001_0015h. Code in user mode waits with UMWAIT or AMD’s MWAITX instead. _mm_monitor and _mm_mwait compile with SSE3 enabled, as in -march=x86-64-v2 and later, to a plain MONITOR and MWAIT with ECX and EAX loaded, in GCC 14 and Clang 23. The probe runs at CPL 3 in a Zen 5 guest that does not report MONITOR, so there are no recorded cases.

Forms

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

if CPL > 0:
    fault(UD)                    # CPL 0 alone (AMD: unless the OS
                                 # sets HWCR's MonMwaitUserEn)
if ecx & ~5:
    fault(GP, 0)                 # ECX bits 31:3 and 1 are reserved;
                                 # 0 and 2 need CPUID 5's say-so
pass                             # rests, in the C-state EAX[7:4] + 1
                                 # asks for (0FH: C0), until a store
                                 # hits the monitored range or an
                                 # event comes; an interrupt even
                                 # with IF clear if ECX[0] is set
# without an armed monitor it does not wait, unless ECX[2] (Intel's
# monitorless MWAIT); either way the monitor is clear after it

Operands

Flags

None: XED records no flag that the forms test or change.

Attributes

What else XED records about the forms. How to read.

All forms

privileged: CPL 0 only; may abort a TSX transaction

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to MWAIT, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More MONITOR/MWAIT instructions

• MONITOR