MWAITX instruction (MONITORX)

Forms

Every encoding of MWAITX that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`MWAITX` MWAITX	`NP 0F 01 FB`	MONITORX

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

if ecx & ~3:
    fault(GP, 0)                 # ECX bits 31:2 are reserved
pass                             # rests, in the C-state EAX[7:4] + 1
                                 # asks for, until a store from
                                 # another processor hits the range
                                 # of MONITORX or an event comes
# ECX[0]: an interrupt ends it even with IF clear; ECX[1]: so does
# EBX ticks of the TSC's clock, if EBX is not 0. Any privilege level;
# it changes no more than NOP does

Not run on a processor: the Zen 5 guest that ran the probe does not report MONITORX in CPUID.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`MWAITX`
`EAX`	implicit	read, write
`ECX`	implicit	read

Flags

None: XED records no flag that the forms test or change.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`MONITORX` MONITORX	MONITORX `CPUID.80000001H:ECX[29]` MONITORX	Zen 2, Zen 3, Zen 4, Zen 5, Zen 6 Note: XED gives MONITORX and MWAITX to its Zen 2 chip alone; GCC's -march=bdver4 (Excavator) and -march=znver1 and later enable them.

More MONITORX instructions

MONITORX