Instruction
NEG
Replaces an operand with its two's complement; APX adds three-operand forms and forms that leave the flags unchanged.
- Extensions
- Forms
- 18 (6 Legacy, 12 EVEX)
- Data
- Intel XED v2026.08.23
Forms
| Instruction | Encoding | Requires |
|---|---|---|
NEG m8
NEG_MEMb | F6 /3 | Base instruction set |
NEG r8
NEG_GPR8 | F6 /3 | Base instruction set |
NEG m16/32/64
NEG_MEMv | F7 /3 | Base instruction set |
NEG r16/32/64
NEG_GPRv | F7 /3 | Base instruction set |
LOCK NEG m8
NEG_LOCK_MEMb | F6 /3 | Base instruction set |
LOCK NEG m16/32/64
NEG_LOCK_MEMv | F7 /3 | Base instruction set |
NEG r8
NEG_GPR8i8_APX | EVEX.LLZ.NP.MAP4.WIG F6 /3 | APX_F |
NEG m8
NEG_MEMi8_APX | EVEX.LLZ.NP.MAP4.WIG F6 /3 | APX_F |
NEG r8 NF
NEG_GPR8i8_APX_N3 | EVEX.LLZ.NP.MAP4.WIG F6 /3 NF=1 | APX_F + APX_NCI_NDD_NF |
NEG m8 NF
NEG_MEMi8_APX_N3 | EVEX.LLZ.NP.MAP4.WIG F6 /3 NF=1 | APX_F + APX_NCI_NDD_NF |
NEG r8, r8 NDD NF optional
NEG_GPR8i8_GPR8i8_APX_N3 | EVEX.LLZ.NP.MAP4.WIG F6 /3 ND=1 NF=0/1 | APX_F + APX_NCI_NDD_NF |
NEG r8, m8 NDD NF optional
NEG_GPR8i8_MEMi8_APX_N3 | EVEX.LLZ.NP.MAP4.WIG F6 /3 ND=1 NF=0/1 | APX_F + APX_NCI_NDD_NF |
NEG r16/32/64
NEG_GPRv_APX | EVEX.LLZ.NP.MAP4.SCALABLE F7 /3 | APX_F |
NEG m16/32/64
NEG_MEMv_APX | EVEX.LLZ.NP.MAP4.SCALABLE F7 /3 | APX_F |
NEG r16/32/64 NF
NEG_GPRv_APX_N3 | EVEX.LLZ.NP.MAP4.SCALABLE F7 /3 NF=1 | APX_F + APX_NCI_NDD_NF |
NEG m16/32/64 NF
NEG_MEMv_APX_N3 | EVEX.LLZ.NP.MAP4.SCALABLE F7 /3 NF=1 | APX_F + APX_NCI_NDD_NF |
NEG r16/32/64, r16/32/64 NDD NF optional
NEG_GPRv_GPRv_APX_N3 | EVEX.LLZ.NP.MAP4.SCALABLE F7 /3 ND=1 NF=0/1 | APX_F + APX_NCI_NDD_NF |
NEG r16/32/64, m16/32/64 NDD NF optional
NEG_GPRv_MEMv_APX_N3 | EVEX.LLZ.NP.MAP4.SCALABLE F7 /3 ND=1 NF=0/1 | APX_F + APX_NCI_NDD_NF |
CPUID and processors
Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.
| ISA set | CPUID | Processors in XED |
|---|---|---|
I86 | No CPUID bit: part of the base instruction set. | Every x86-64 processor in XED’s model |
APX_F | APX_F | Nova Lake, Diamond Rapids |
APX_F_N3 | APX_F + APX_NCI_NDD_NF | Nova Lake, Diamond Rapids |
More General-purpose instructions
- JECXZ
- JMP
- JRCXZ
- LDS
- LEA
- LEAVE
- LES
- LFS
- LGS
- LODS
- LOOP
- LOOPE
- LOOPNE
- LSS
- MOV
- MOVS
- MOVSX
- MOVSXD
- MOVZX
- MUL
- NOP
- NOT
- OR
- OUT
- OUTS
- PAUSE
- POP
- POPA
- POPF
- PUSH
- PUSHA
- PUSHF
- RCL
- RCR
- RET
- ROL
- ROR
- SALC
- SAR
- SBB
All 109 General-purpose instructions
More APX instructions
Sources
- Intel XED v2026.08.23 (commit
0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model. - Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-092, June 2026)
- Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026)
- Intel Advanced Performance Extensions (Intel APX) Architecture Specification, revision 7.0 (July 2025)
The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The text is our own.