Extensions
Forms
18 (6 Legacy, 12 EVEX)
Data
Intel XED v2026.08.23

NEG replaces its operand with 0 minus the operand, the two’s complement, and sets the flags as that subtraction would. Two consequences are easy to miss:

  • CF tells whether the operand was nonzero. Subtracting anything but 0 from 0 borrows, so NEG sets CF for every operand except 0.
  • The most negative number stays as it is. For 64 bits, -2^63 has no positive counterpart, so NEG leaves it unchanged and sets OF; that is the only operand for which OF is set.

In compiled code

GCC 14 and Clang 23 at -O2 compile -x to a NEG, and use its flags in three places:

  • Absolute value. labs(x) becomes mov rax, rdi, neg rax and cmovs rax, rdi: when the negated value is negative, x was positive and is kept. For the most negative x both values are the same, and so is the result, which C leaves undefined.
  • A mask from “nonzero”. Both compilers end x ? -1 : 0 with neg edi and sbb eax, eax: SBB of a register from itself turns the CF that NEG set into all ones or all zeros, without a branch.
  • Wide negation. For an __int128, NEG negates the low half and its CF is the borrow into the high half: both compilers emit xor edx, edx, neg rax and sbb rdx, rsi, which subtracts the high half and the borrow from 0.

NEG also appears in the idioms of other instructions: x & -x, which keeps the lowest set bit, is NEG and AND (or BLSI), and an atomic_fetch_sub whose old value is used becomes NEG and LOCK XADD, since x86 has no exchanging subtraction. NOT differs from NEG by one: ~x equals -x - 1.

Forms

Every encoding of NEG that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
NEG m8 NEG_MEMbF6 /3Base instruction set
NEG r8 NEG_GPR8F6 /3Base instruction set
NEG m16/32/64 NEG_MEMvF7 /3Base instruction set
NEG r16/32/64 NEG_GPRvF7 /3Base instruction set
LOCK NEG m8 NEG_LOCK_MEMbF6 /3Base instruction set
LOCK NEG m16/32/64 NEG_LOCK_MEMvF7 /3Base instruction set
NEG r8 NEG_GPR8i8_APXEVEX.LLZ.NP.MAP4.WIG F6 /3APX_F
NEG m8 NEG_MEMi8_APXEVEX.LLZ.NP.MAP4.WIG F6 /3APX_F
NEG r8 NF NEG_GPR8i8_APX_N3EVEX.LLZ.NP.MAP4.WIG F6 /3 NF=1APX_F + APX_NCI_NDD_NF
NEG m8 NF NEG_MEMi8_APX_N3EVEX.LLZ.NP.MAP4.WIG F6 /3 NF=1APX_F + APX_NCI_NDD_NF
NEG r8, r8 NDD NF optional NEG_GPR8i8_GPR8i8_APX_N3EVEX.LLZ.NP.MAP4.WIG F6 /3 ND=1 NF=0/1APX_F + APX_NCI_NDD_NF
NEG r8, m8 NDD NF optional NEG_GPR8i8_MEMi8_APX_N3EVEX.LLZ.NP.MAP4.WIG F6 /3 ND=1 NF=0/1APX_F + APX_NCI_NDD_NF
NEG r16/32/64 NEG_GPRv_APXEVEX.LLZ.NP.MAP4.SCALABLE F7 /3APX_F
NEG m16/32/64 NEG_MEMv_APXEVEX.LLZ.NP.MAP4.SCALABLE F7 /3APX_F
NEG r16/32/64 NF NEG_GPRv_APX_N3EVEX.LLZ.NP.MAP4.SCALABLE F7 /3 NF=1APX_F + APX_NCI_NDD_NF
NEG m16/32/64 NF NEG_MEMv_APX_N3EVEX.LLZ.NP.MAP4.SCALABLE F7 /3 NF=1APX_F + APX_NCI_NDD_NF
NEG r16/32/64, r16/32/64 NDD NF optional NEG_GPRv_GPRv_APX_N3EVEX.LLZ.NP.MAP4.SCALABLE F7 /3 ND=1 NF=0/1APX_F + APX_NCI_NDD_NF
NEG r16/32/64, m16/32/64 NDD NF optional NEG_GPRv_MEMv_APX_N3EVEX.LLZ.NP.MAP4.SCALABLE F7 /3 ND=1 NF=0/1APX_F + APX_NCI_NDD_NF

Latency and throughput

What the scheduling models of LLVM 23.1.2 give for each form, not measurements: latency / reciprocal throughput in cycles, the ports under them. A row is a model, or models that agree; a dash, a form that its processors lack. Memory forms: latency from the address, ports without the load and store units. Which processors each model covers.
Modelm8r8
r16
r32
r64
m16
m32
m64
NEG m8NEG m16
NEG m32
NEG m64
Sandy Bridge7 / 1p0151 / 0.33p0157 / 1p0157 / 1p0157 / 1p015
Haswell, Broadwell, Skylake, Skylake-SP7 / 1p01561 / 0.25p01567 / 1p01567 / 1p01567 / 1p0156
Ice Lake7 / 0.5p01561 / 0.25p01567 / 0.5p01567 / 0.5p01567 / 0.5p0156
Alder Lake, Sapphire Rapids13 / 0.5p0 p1 p5 p6 p111 / 0.2p0 p1 p5 p6 p1112 / 0.5p0 p1 p5 p6 p1113 / 0.5p0 p1 p5 p6 p1112 / 0.5p0 p1 p5 p6 p11
Lunar Lake13 / 0.5p0123451 / 0.33p13512 / 0.67p13513 / 0.5p01234512 / 0.67p135
Bonnell1 / 1p01 / 0.5p011 / 1p01 / 1p01 / 1p0
Silvermont5 / 2IEC0 IEC1 MEC1 / 0.5IEC0 IEC15 / 2IEC0 IEC1 MEC5 / 2IEC0 IEC1 MEC5 / 2IEC0 IEC1 MEC
Piledriver6 / 2EX0 EX11 / 1EX0 EX16 / 2EX0 EX16 / 2EX0 EX16 / 2EX0 EX1
Zen5 / 0.5ALU0 ALU1 ALU2 ALU31 / 0.25ALU0 ALU1 ALU2 ALU35 / 0.5ALU0 ALU1 ALU2 ALU35 / 0.5ALU0 ALU1 ALU2 ALU35 / 0.5ALU0 ALU1 ALU2 ALU3
Zen 25 / 0.33ALU0 ALU1 ALU2 ALU31 / 0.25ALU0 ALU1 ALU2 ALU35 / 0.33ALU0 ALU1 ALU2 ALU35 / 0.33ALU0 ALU1 ALU2 ALU35 / 0.33ALU0 ALU1 ALU2 ALU3
Zen 3, Zen 46 / 0.67ALU0 ALU1 ALU2 ALU31 / 0.25ALU0 ALU1 ALU2 ALU36 / 0.67ALU0 ALU1 ALU2 ALU36 / 0.67ALU0 ALU1 ALU2 ALU36 / 0.67ALU0 ALU1 ALU2 ALU3
Jaguar6 / 1ALU0 ALU11 / 0.5ALU0 ALU16 / 1ALU0 ALU119 / 19ALU0 ALU119 / 19ALU0 ALU1

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

All forms but the NDD forms
a = dest.read()                  # with LOCK: one atomic read-modify-write
if not nf:                       # NF=1 (APX) leaves the flags as they were
    flags = sub_flags(0, a)      # as 0 - a: CF is 1 unless a is 0
dest.write(-a)                   # the smallest negative number stays as it
                                 # is, with OF set

Run on AMD Zen 5 (EPYC 9645): 72 cases. The APX forms were not run: none of these processors has APX.

NDD forms
a = src.read()
if not nf:                       # NF=1 leaves the flags as they were
    flags = sub_flags(0, a)      # as 0 - a: CF is 1 unless a is 0
dest.write(-a)                   # the new destination: bits 63:OSIZE
                                 # cleared, even for 8 and 16 bits

Not run on a processor: none of these processors has APX.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.
OperandKindAction
NEG r/m8 NEG r/m16/32/64 LOCK NEG m8 LOCK NEG m16/32/64
r/m8/16/32/64explicitread, write
RFLAGSimplicitwrite
NEG r/m8 NF NEG r/m16/32/64 NF
r/m8/16/32/64explicitread, write
NEG r8, r/m8 NDD NF optional NEG r16/32/64, r/m16/32/64 NDD NF optional
r8/16/32/64explicitwrite
r/m8/16/32/64explicitread
RFLAGSimplicitwrite (NF=0)

Flags

M modified; blank: not affected. With NF=1, the forms with optional NF leave the flags unchanged. How to read.
WhenOFSFZFAFPFCF
NF forms
Not affected
NDD forms
NF=0MMMMMM
Other forms
MMMMMM

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

Legacy forms
none in XED
EVEX forms
APX-EVEX-INT

Attributes

What else XED records about the forms. How to read.

Legacy memory forms without LOCK
accepts a LOCK prefix
LOCK forms
locked: atomic read-modify-write; accepts XACQUIRE; accepts XRELEASE

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.
ISA setCPUIDProcessors
I86

No CPUID bit: part of the base instruction set.

Every x86-64 processor in XED’s model and Zen 3 to Zen 6
APX_F

APX_F
CPUID.(EAX=07H,ECX=1):EDX[21] APX_F

Nova Lake, Diamond Rapids
APX_F_N3

APX_F + APX_NCI_NDD_NF
CPUID.(EAX=07H,ECX=1):EDX[21] APX_F
CPUID.(EAX=29H,ECX=0):EBX[0] APX_NCI_NDD_NF

Same as APX_F

More General-purpose instructions

All 109 General-purpose instructions

More APX instructions

All 88 APX instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, operands, flags, exception classes, attributes, ISA sets, CPUID bits and chip model.
  2. The CPU data of x86-64.net: Zen 3 to Zen 6, from GCC’s -march feature sets and AMD’s Processor Programming References, which the page of each processor cites.
  3. LLVM 23.1.2's x86 scheduling models (commit 85ac56026243): the latency, reciprocal throughput and ports of each form, as llvm-mca reports them.
  4. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026): Volume 2B, page 4-158 (NEG)
  5. Intel Advanced Performance Extensions (Intel APX) Architecture Specification, revision 9.0 (355828-009, August 2026)
  6. AMD64 Architecture Programmer's Manual, Volume 3: General-Purpose and System Instructions (24594, rev. 3.39, October 2026)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The timings come from LLVM's scheduling models, part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.