x86-64.net

Instruction

NOP

Does nothing: 90 and the multi-byte 0F 1F forms pad code for alignment, and other opcodes of 0F 18 to 0F 1F are reserved to decode as NOPs.

Extensions
Forms
28 (28 Legacy)
Data
Intel XED v2026.08.23

Forms

Every encoding of NOP that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
NOP r16/32/64 NOP_GPRv_0F18r00F 18 /0Base instruction set
NOP r16/32/64 NOP_GPRv_0F18r10F 18 /1Base instruction set
NOP r16/32/64 NOP_GPRv_0F18r20F 18 /2Base instruction set
NOP r16/32/64 NOP_GPRv_0F18r30F 18 /3Base instruction set
NOP r16/32/64 NOP_GPRv_0F18r40F 18 /4Base instruction set
NOP m16/32/64 NOP_MEMv_0F18r50F 18 /5Base instruction set
NOP r16/32/64 NOP_GPRv_0F18r50F 18 /5Base instruction set
NOP r16/32/64 NOP_GPRv_0F18r60F 18 /6Base instruction set
NOP r16/32/64 NOP_GPRv_0F18r70F 18 /7Base instruction set
NOP m16/32/64 NOP_MEMv_0F18r40F 18 /4 (without MOVRS)Base instruction set
NOP m16/32/64 NOP_MEMv_0F18r60F 18 /6 (without PREFETCHI)Base instruction set
NOP m16/32/64 NOP_MEMv_0F18r70F 18 /7 (without PREFETCHI)Base instruction set
NOP m16/32/64, r16/32/64 NOP_MEMv_GPRv_0F190F 19 /rBase instruction set
NOP r16/32/64, r16/32/64 NOP_GPRv_GPRv_0F190F 19 /rBase instruction set
NOP m16/32/64, r16/32/64 NOP_MEMv_GPRv_0F1D0F 1D /rBase instruction set
NOP r16/32/64, r16/32/64 NOP_GPRv_GPRv_0F1D0F 1D /rBase instruction set
NOP m16/32/64 NOP_MEMv_0F1F0F 1F /rBase instruction set
NOP r16/32/64 NOP_GPRv_0F1F0F 1F /rBase instruction set
NOP NOP_9090Base instruction set
NOP r16/32/64, r16/32/64 NOP_GPRv_GPRv_0F0D0F 0D /rBase instruction set
NOP m16/32/64, r16/32/64 NOP_MEMv_GPRv_0F1CF2 0F 1C /0
66 0F 1C /0
66 0F 1C /r
F3 0F 1C /0
F2 0F 1C /r
F3 0F 1C /r
NP 0F 1C /r
NP 0F 1C /0 (without CLDEMOTE)		Base instruction set
NOP r16/32/64, r16/32/64 NOP_GPRv_GPRv_0F1C0F 1C /rBase instruction set
NOP r16/32/64, r16/32/64 NOP_GPRv_GPRv_0F1ANP 0F 1A /r
0F 1A /r (without MPX)		Base instruction set
NOP r16/32/64, r16/32/64 NOP_GPRv_GPRv_0F1BNP 0F 1B /r
F3 0F 1B /r
0F 1B /r (without MPX)		Base instruction set
NOP r16/32/64, m16/32/64 NOP_GPRv_MEMv_0F1A0F 1A /r (without MPX)Base instruction set
NOP r16/32/64, m16/32/64 NOP_GPRv_MEM_0F1B0F 1B /r (without MPX)Base instruction set
NOP m16/32/64, r16/32/64 NOP_MEMv_GPRv_0F1E0F 1E /rBase instruction set
NOP r16/32/64, r16/32/64 NOP_GPRv_GPRv_0F1ENP 0F 1E /r
66 0F 1E /r
F2 0F 1E /r
F3 0F 1E /0
F3 0F 1E /2
F3 0F 1E /3
F3 0F 1E /4
F3 0F 1E /5
F3 0F 1E F9
F3 0F 1E FD
F3 0F 1E FE
F3 0F 1E FF
F3 0F 1E /6
F3 0F 1E FC
F3 0F 1E FA (without CET)
F3 0F 1E FB (without CET)
F3 0F 1E /1 (without CET)
F3 REX.W 0F 1E /1 (without CET)
F3 REX.W 0F 1E F8 (without IBHF)
F3 0F 1E F8		Base instruction set

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, which covers AMD processors up to Zen 2.
ISA setCPUIDProcessors in XED
FAT_NOP

No CPUID bit: part of the base instruction set.

Every x86-64 processor in XED’s model
I86

No CPUID bit: part of the base instruction set.

Every x86-64 processor in XED’s model
PREFETCH_NOP

No CPUID bit: part of the base instruction set.

Every x86-64 processor in XED’s model
PPRO

No CPUID bit: part of the base instruction set.

Every x86-64 processor in XED’s model

More General-purpose instructions

All 109 General-purpose instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model.
  2. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-092, June 2026)
  3. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The text is our own.