Instruction
NOT
Inverts every bit of an operand without changing the flags; APX adds a three-operand form.
- Extensions
- Forms
- 14 (6 Legacy, 8 EVEX)
- Data
- Intel XED v2026.08.23
NOT inverts every bit of its operand, which is C’s ~x. Unlike AND, OR,
XOR and NEG, it leaves all the flags alone, so it can sit between an
instruction that sets them and the branch that reads them.
NOT and its relatives
- XOR with -1 computes the same value but writes the flags, and in a
64-bit register takes a byte more. GCC 14 and Clang 23 at -O2 compile
both
~xandx ^ -1tonot rax. - NEG is the two’s complement, so the two differ by one:
~x == -x - 1. Both compilers compile-x - 1and-(x + 1)to NOT, and~x + 1to NEG. - Logical negation, C’s
!x, is a comparison, not NOT: both emitxor eax, eax,test edi, ediandsete al. - AND with an inverted operand,
~a & b, is a NOT and an AND, or one ANDN when BMI1 is enabled.
Memory and LOCK
NOT can invert memory in place (*p = ~*p becomes
not qword ptr [rdi]), and with LOCK it does so atomically. C has no
atomic NOT, and compilers do not reach for LOCK NOT: both compile
atomic_fetch_xor(p, -1) to lock xor qword ptr [rdi], -1 when the
result is unused, and to a CMPXCHG loop with a NOT
inside when it is used.
Other registers
Vector registers have no NOT: compilers XOR with all ones, which SSE code makes with PCMPEQD of a register with itself, and AVX-512 code uses VPTERNLOGD or VPTERNLOGQ with the register in all three operands. The mask registers have their own, KNOTW and its kin.
Forms
| Instruction | Encoding | Requires |
|---|---|---|
NOT m8
NOT_MEMb | F6 /2 | Base instruction set |
NOT r8
NOT_GPR8 | F6 /2 | Base instruction set |
NOT m16/32/64
NOT_MEMv | F7 /2 | Base instruction set |
NOT r16/32/64
NOT_GPRv | F7 /2 | Base instruction set |
LOCK NOT m8
NOT_LOCK_MEMb | F6 /2 | Base instruction set |
LOCK NOT m16/32/64
NOT_LOCK_MEMv | F7 /2 | Base instruction set |
NOT r8
NOT_GPR8i8_APX | EVEX.LLZ.NP.MAP4.WIG F6 /2 | APX_F |
NOT m8
NOT_MEMi8_APX | EVEX.LLZ.NP.MAP4.WIG F6 /2 | APX_F |
NOT r8, r8 NDD
NOT_GPR8i8_GPR8i8_APX_N3 | EVEX.LLZ.NP.MAP4.WIG F6 /2 ND=1 | APX_F + APX_NCI_NDD_NF |
NOT r8, m8 NDD
NOT_GPR8i8_MEMi8_APX_N3 | EVEX.LLZ.NP.MAP4.WIG F6 /2 ND=1 | APX_F + APX_NCI_NDD_NF |
NOT r16/32/64
NOT_GPRv_APX | EVEX.LLZ.NP.MAP4.SCALABLE F7 /2 | APX_F |
NOT m16/32/64
NOT_MEMv_APX | EVEX.LLZ.NP.MAP4.SCALABLE F7 /2 | APX_F |
NOT r16/32/64, r16/32/64 NDD
NOT_GPRv_GPRv_APX_N3 | EVEX.LLZ.NP.MAP4.SCALABLE F7 /2 ND=1 | APX_F + APX_NCI_NDD_NF |
NOT r16/32/64, m16/32/64 NDD
NOT_GPRv_MEMv_APX_N3 | EVEX.LLZ.NP.MAP4.SCALABLE F7 /2 ND=1 | APX_F + APX_NCI_NDD_NF |
Latency and throughput
| Model | m8 | r8r16r32r64 | m16m32m64 | NOT m8 | NOT m16NOT m32NOT m64 |
|---|---|---|---|---|---|
| Sandy Bridge | 7 / 1p015 | 1 / 0.33p015 | 7 / 1p015 | 7 / 1p015 | 7 / 1p015 |
| Haswell, Broadwell, Skylake, Skylake-SP | 7 / 1p0156 | 1 / 0.25p0156 | 7 / 1p0156 | 7 / 1p0156 | 7 / 1p0156 |
| Ice Lake | 7 / 0.5p0156 | 1 / 0.25p0156 | 7 / 0.5p0156 | 7 / 0.5p0156 | 7 / 0.5p0156 |
| Alder Lake, Sapphire Rapids | 13 / 0.5p0 p1 p5 p6 p11 | 1 / 0.2p0 p1 p5 p6 p11 | 12 / 0.5p0 p1 p5 p6 p11 | 13 / 0.5p0 p1 p5 p6 p11 | 12 / 0.5p0 p1 p5 p6 p11 |
| Lunar Lake | 13 / 0.5p012345 | 1 / 0.33p135 | 12 / 0.67p135 | 13 / 0.5p012345 | 12 / 0.67p135 |
| Bonnell | 1 / 1p0 | 1 / 0.5p01 | 1 / 1p0 | 1 / 1p0 | 1 / 1p0 |
| Silvermont | 5 / 2IEC0 IEC1 MEC | 1 / 0.5IEC0 IEC1 | 5 / 2IEC0 IEC1 MEC | 5 / 2IEC0 IEC1 MEC | 5 / 2IEC0 IEC1 MEC |
| Piledriver | 6 / 2EX0 EX1 | 1 / 1EX0 EX1 | 6 / 2EX0 EX1 | 6 / 2EX0 EX1 | 6 / 2EX0 EX1 |
| Zen | 5 / 0.5ALU0 ALU1 ALU2 ALU3 | 1 / 0.25ALU0 ALU1 ALU2 ALU3 | 5 / 0.5ALU0 ALU1 ALU2 ALU3 | 5 / 0.5ALU0 ALU1 ALU2 ALU3 | 5 / 0.5ALU0 ALU1 ALU2 ALU3 |
| Zen 2 | 5 / 0.33ALU0 ALU1 ALU2 ALU3 | 1 / 0.25ALU0 ALU1 ALU2 ALU3 | 5 / 0.33ALU0 ALU1 ALU2 ALU3 | 5 / 0.33ALU0 ALU1 ALU2 ALU3 | 5 / 0.33ALU0 ALU1 ALU2 ALU3 |
| Zen 3, Zen 4 | 6 / 0.67ALU0 ALU1 ALU2 ALU3 | 1 / 0.25ALU0 ALU1 ALU2 ALU3 | 6 / 0.67ALU0 ALU1 ALU2 ALU3 | 6 / 0.67ALU0 ALU1 ALU2 ALU3 | 6 / 0.67ALU0 ALU1 ALU2 ALU3 |
| Jaguar | 6 / 1ALU0 ALU1 | 1 / 0.5ALU0 ALU1 | 6 / 1ALU0 ALU1 | 19 / 19ALU0 ALU1 | 19 / 19ALU0 ALU1 |
Operation
What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.
dest.write(~dest) # with LOCK: one atomic read-modify-write;
# no flag changes
Run on AMD Zen 5 (EPYC 9645): 72 cases. The APX forms were not run: none of these processors has APX.
dest.write(~src) # the new destination: bits 63:OSIZE
# cleared, even for 8 and 16 bits
Not run on a processor: none of these processors has APX.
Operands
| Operand | Kind | Action |
|---|---|---|
NOT r/m8 NOT r/m16/32/64 LOCK NOT m8 LOCK NOT m16/32/64 | ||
r/m8/16/32/64 | explicit | read, write |
NOT r8, r/m8 NDD NOT r16/32/64, r/m16/32/64 NDD | ||
r8/16/32/64 | explicit | write |
r/m8/16/32/64 | explicit | read |
Flags
None: XED records no flag that the forms test or change.
Exceptions
The exception class is XED's name for the set of exception conditions that a form follows. How to read.
- Legacy forms
- none in XED
- EVEX forms
APX-EVEX-INT
Attributes
What else XED records about the forms. How to read.
- Legacy memory forms without LOCK
- accepts a LOCK prefix
- LOCK forms
- locked: atomic read-modify-write; accepts XACQUIRE; accepts XRELEASE
CPUID and processors
Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.
| ISA set | CPUID | Processors |
|---|---|---|
I86 | No CPUID bit: part of the base instruction set. | Every x86-64 processor in XED’s model and Zen 3 to Zen 6 |
APX_F | APX_F | Nova Lake, Diamond Rapids |
APX_F_N3 | APX_F + APX_NCI_NDD_NF | Same as APX_F |
More General-purpose instructions
- JRCXZ
- LDS
- LEA
- LEAVE
- LES
- LFS
- LGS
- LODS
- LOOP
- LOOPE
- LOOPNE
- LSS
- MOV
- MOVS
- MOVSX
- MOVSXD
- MOVZX
- MUL
- NEG
- NOP
- OR
- OUT
- OUTS
- PAUSE
- POP
- POPA
- POPF
- PUSH
- PUSHA
- PUSHF
- RCL
- RCR
- RET
- ROL
- ROR
- SALC
- SAR
- SBB
- SCAS
- SETcc
All 109 General-purpose instructions
More APX instructions
Sources
- Intel XED v2026.08.23 (commit
0bcb6237345c): forms, encodings, operands, flags, exception classes, attributes, ISA sets, CPUID bits and chip model. - The CPU data of x86-64.net: Zen 3 to Zen 6, from GCC’s
-marchfeature sets and AMD’s Processor Programming References, which the page of each processor cites. - LLVM 23.1.2's x86 scheduling models (commit
85ac56026243): the latency, reciprocal throughput and ports of each form, as llvm-mca reports them. - Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026): Volume 2B, page 4-161 (NOT)
- Intel Advanced Performance Extensions (Intel APX) Architecture Specification, revision 9.0 (355828-009, August 2026)
- AMD64 Architecture Programmer's Manual, Volume 3: General-Purpose and System Instructions (24594, rev. 3.39, October 2026)
The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The timings come from LLVM's scheduling models, part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.