Extensions
Forms
14 (6 Legacy, 8 EVEX)
Data
Intel XED v2026.08.23

NOT inverts every bit of its operand, which is C’s ~x. Unlike AND, OR, XOR and NEG, it leaves all the flags alone, so it can sit between an instruction that sets them and the branch that reads them.

NOT and its relatives

  • XOR with -1 computes the same value but writes the flags, and in a 64-bit register takes a byte more. GCC 14 and Clang 23 at -O2 compile both ~x and x ^ -1 to not rax.
  • NEG is the two’s complement, so the two differ by one: ~x == -x - 1. Both compilers compile -x - 1 and -(x + 1) to NOT, and ~x + 1 to NEG.
  • Logical negation, C’s !x, is a comparison, not NOT: both emit xor eax, eax, test edi, edi and sete al.
  • AND with an inverted operand, ~a & b, is a NOT and an AND, or one ANDN when BMI1 is enabled.

Memory and LOCK

NOT can invert memory in place (*p = ~*p becomes not qword ptr [rdi]), and with LOCK it does so atomically. C has no atomic NOT, and compilers do not reach for LOCK NOT: both compile atomic_fetch_xor(p, -1) to lock xor qword ptr [rdi], -1 when the result is unused, and to a CMPXCHG loop with a NOT inside when it is used.

Other registers

Vector registers have no NOT: compilers XOR with all ones, which SSE code makes with PCMPEQD of a register with itself, and AVX-512 code uses VPTERNLOGD or VPTERNLOGQ with the register in all three operands. The mask registers have their own, KNOTW and its kin.

Forms

Every encoding of NOT that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
NOT m8 NOT_MEMbF6 /2Base instruction set
NOT r8 NOT_GPR8F6 /2Base instruction set
NOT m16/32/64 NOT_MEMvF7 /2Base instruction set
NOT r16/32/64 NOT_GPRvF7 /2Base instruction set
LOCK NOT m8 NOT_LOCK_MEMbF6 /2Base instruction set
LOCK NOT m16/32/64 NOT_LOCK_MEMvF7 /2Base instruction set
NOT r8 NOT_GPR8i8_APXEVEX.LLZ.NP.MAP4.WIG F6 /2APX_F
NOT m8 NOT_MEMi8_APXEVEX.LLZ.NP.MAP4.WIG F6 /2APX_F
NOT r8, r8 NDD NOT_GPR8i8_GPR8i8_APX_N3EVEX.LLZ.NP.MAP4.WIG F6 /2 ND=1APX_F + APX_NCI_NDD_NF
NOT r8, m8 NDD NOT_GPR8i8_MEMi8_APX_N3EVEX.LLZ.NP.MAP4.WIG F6 /2 ND=1APX_F + APX_NCI_NDD_NF
NOT r16/32/64 NOT_GPRv_APXEVEX.LLZ.NP.MAP4.SCALABLE F7 /2APX_F
NOT m16/32/64 NOT_MEMv_APXEVEX.LLZ.NP.MAP4.SCALABLE F7 /2APX_F
NOT r16/32/64, r16/32/64 NDD NOT_GPRv_GPRv_APX_N3EVEX.LLZ.NP.MAP4.SCALABLE F7 /2 ND=1APX_F + APX_NCI_NDD_NF
NOT r16/32/64, m16/32/64 NDD NOT_GPRv_MEMv_APX_N3EVEX.LLZ.NP.MAP4.SCALABLE F7 /2 ND=1APX_F + APX_NCI_NDD_NF

Latency and throughput

What the scheduling models of LLVM 23.1.2 give for each form, not measurements: latency / reciprocal throughput in cycles, the ports under them. A row is a model, or models that agree; a dash, a form that its processors lack. Memory forms: latency from the address, ports without the load and store units. Which processors each model covers.
Modelm8r8
r16
r32
r64
m16
m32
m64
NOT m8NOT m16
NOT m32
NOT m64
Sandy Bridge7 / 1p0151 / 0.33p0157 / 1p0157 / 1p0157 / 1p015
Haswell, Broadwell, Skylake, Skylake-SP7 / 1p01561 / 0.25p01567 / 1p01567 / 1p01567 / 1p0156
Ice Lake7 / 0.5p01561 / 0.25p01567 / 0.5p01567 / 0.5p01567 / 0.5p0156
Alder Lake, Sapphire Rapids13 / 0.5p0 p1 p5 p6 p111 / 0.2p0 p1 p5 p6 p1112 / 0.5p0 p1 p5 p6 p1113 / 0.5p0 p1 p5 p6 p1112 / 0.5p0 p1 p5 p6 p11
Lunar Lake13 / 0.5p0123451 / 0.33p13512 / 0.67p13513 / 0.5p01234512 / 0.67p135
Bonnell1 / 1p01 / 0.5p011 / 1p01 / 1p01 / 1p0
Silvermont5 / 2IEC0 IEC1 MEC1 / 0.5IEC0 IEC15 / 2IEC0 IEC1 MEC5 / 2IEC0 IEC1 MEC5 / 2IEC0 IEC1 MEC
Piledriver6 / 2EX0 EX11 / 1EX0 EX16 / 2EX0 EX16 / 2EX0 EX16 / 2EX0 EX1
Zen5 / 0.5ALU0 ALU1 ALU2 ALU31 / 0.25ALU0 ALU1 ALU2 ALU35 / 0.5ALU0 ALU1 ALU2 ALU35 / 0.5ALU0 ALU1 ALU2 ALU35 / 0.5ALU0 ALU1 ALU2 ALU3
Zen 25 / 0.33ALU0 ALU1 ALU2 ALU31 / 0.25ALU0 ALU1 ALU2 ALU35 / 0.33ALU0 ALU1 ALU2 ALU35 / 0.33ALU0 ALU1 ALU2 ALU35 / 0.33ALU0 ALU1 ALU2 ALU3
Zen 3, Zen 46 / 0.67ALU0 ALU1 ALU2 ALU31 / 0.25ALU0 ALU1 ALU2 ALU36 / 0.67ALU0 ALU1 ALU2 ALU36 / 0.67ALU0 ALU1 ALU2 ALU36 / 0.67ALU0 ALU1 ALU2 ALU3
Jaguar6 / 1ALU0 ALU11 / 0.5ALU0 ALU16 / 1ALU0 ALU119 / 19ALU0 ALU119 / 19ALU0 ALU1

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

All forms but the NDD forms
dest.write(~dest)                # with LOCK: one atomic read-modify-write;
                                 # no flag changes

Run on AMD Zen 5 (EPYC 9645): 72 cases. The APX forms were not run: none of these processors has APX.

NDD forms
dest.write(~src)                 # the new destination: bits 63:OSIZE
                                 # cleared, even for 8 and 16 bits

Not run on a processor: none of these processors has APX.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.
OperandKindAction
NOT r/m8 NOT r/m16/32/64 LOCK NOT m8 LOCK NOT m16/32/64
r/m8/16/32/64explicitread, write
NOT r8, r/m8 NDD NOT r16/32/64, r/m16/32/64 NDD
r8/16/32/64explicitwrite
r/m8/16/32/64explicitread

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

Legacy forms
none in XED
EVEX forms
APX-EVEX-INT

Attributes

What else XED records about the forms. How to read.

Legacy memory forms without LOCK
accepts a LOCK prefix
LOCK forms
locked: atomic read-modify-write; accepts XACQUIRE; accepts XRELEASE

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.
ISA setCPUIDProcessors
I86

No CPUID bit: part of the base instruction set.

Every x86-64 processor in XED’s model and Zen 3 to Zen 6
APX_F

APX_F
CPUID.(EAX=07H,ECX=1):EDX[21] APX_F

Nova Lake, Diamond Rapids
APX_F_N3

APX_F + APX_NCI_NDD_NF
CPUID.(EAX=07H,ECX=1):EDX[21] APX_F
CPUID.(EAX=29H,ECX=0):EBX[0] APX_NCI_NDD_NF

Same as APX_F

More General-purpose instructions

All 109 General-purpose instructions

More APX instructions

All 88 APX instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, operands, flags, exception classes, attributes, ISA sets, CPUID bits and chip model.
  2. The CPU data of x86-64.net: Zen 3 to Zen 6, from GCC’s -march feature sets and AMD’s Processor Programming References, which the page of each processor cites.
  3. LLVM 23.1.2's x86 scheduling models (commit 85ac56026243): the latency, reciprocal throughput and ports of each form, as llvm-mca reports them.
  4. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026): Volume 2B, page 4-161 (NOT)
  5. Intel Advanced Performance Extensions (Intel APX) Architecture Specification, revision 9.0 (355828-009, August 2026)
  6. AMD64 Architecture Programmer's Manual, Volume 3: General-Purpose and System Instructions (24594, rev. 3.39, October 2026)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The timings come from LLVM's scheduling models, part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.