x86-64.net

Instruction

NOT

Inverts every bit of an operand without changing the flags; APX adds a three-operand form.

Extensions
Forms
14 (6 Legacy, 8 EVEX)
Data
Intel XED v2026.08.23

Forms

Every encoding of NOT that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
NOT m8 NOT_MEMbF6 /2Base instruction set
NOT r8 NOT_GPR8F6 /2Base instruction set
NOT m16/32/64 NOT_MEMvF7 /2Base instruction set
NOT r16/32/64 NOT_GPRvF7 /2Base instruction set
LOCK NOT m8 NOT_LOCK_MEMbF6 /2Base instruction set
LOCK NOT m16/32/64 NOT_LOCK_MEMvF7 /2Base instruction set
NOT r8 NOT_GPR8i8_APXEVEX.LLZ.NP.MAP4.WIG F6 /2APX_F
NOT m8 NOT_MEMi8_APXEVEX.LLZ.NP.MAP4.WIG F6 /2APX_F
NOT r8, r8 NDD NOT_GPR8i8_GPR8i8_APX_N3EVEX.LLZ.NP.MAP4.WIG F6 /2 ND=1APX_F + APX_NCI_NDD_NF
NOT r8, m8 NDD NOT_GPR8i8_MEMi8_APX_N3EVEX.LLZ.NP.MAP4.WIG F6 /2 ND=1APX_F + APX_NCI_NDD_NF
NOT r16/32/64 NOT_GPRv_APXEVEX.LLZ.NP.MAP4.SCALABLE F7 /2APX_F
NOT m16/32/64 NOT_MEMv_APXEVEX.LLZ.NP.MAP4.SCALABLE F7 /2APX_F
NOT r16/32/64, r16/32/64 NDD NOT_GPRv_GPRv_APX_N3EVEX.LLZ.NP.MAP4.SCALABLE F7 /2 ND=1APX_F + APX_NCI_NDD_NF
NOT r16/32/64, m16/32/64 NDD NOT_GPRv_MEMv_APX_N3EVEX.LLZ.NP.MAP4.SCALABLE F7 /2 ND=1APX_F + APX_NCI_NDD_NF

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to NOT, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

IntrinsicCompiles to
_knot_mask32 __mmask32 _knot_mask32(__mmask32 __M)

NOT r16/32/64 Legacy -mavx512bw

_knot_mask64 __mmask64 _knot_mask64(__mmask64 __M)

NOT r16/32/64 Legacy -mavx512bw

_knot_mask8 __mmask8 _knot_mask8(__mmask8 __M)

NOT r8 Legacy -mavx512dq

_mm512_knot __mmask16 _mm512_knot(__mmask16 __M)

NOT r16/32/64 Legacy -mavx512f

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, which covers AMD processors up to Zen 2.
ISA setCPUIDProcessors in XED
I86

No CPUID bit: part of the base instruction set.

Every x86-64 processor in XED’s model
APX_F

APX_F
CPUID.(EAX=07H,ECX=1):EDX[21] APX_F

Nova Lake, Diamond Rapids
APX_F_N3

APX_F + APX_NCI_NDD_NF
CPUID.(EAX=07H,ECX=1):EDX[21] APX_F
CPUID.(EAX=29H,ECX=0):EBX[0] APX_NCI_NDD_NF

Nova Lake, Diamond Rapids

More General-purpose instructions

All 109 General-purpose instructions

More APX instructions

All 88 APX instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model.
  2. Clang's x86 intrinsic headers, LLVM 23.1.2 (commit 85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them.
  3. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-092, June 2026)
  4. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026)
  5. Intel Advanced Performance Extensions (Intel APX) Architecture Specification, revision 7.0 (July 2025)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang, part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.