OR

OR sets the bits of its destination that are set in the source and keeps the others.

Setting bits#

A constant mask is an immediate of at most 32 bits, sign-extended: GCC 14 and Clang 23 at -O2 compile x | 8 to or rax, 8. For a bit whose number is in a register, both use BTS instead, so x | (1ul << n) becomes bts rax, rsi.

Where the bits of the two operands cannot overlap, OR and ADD give the same result, and a compiler may pick either. Joining two bytes, (uint64_t)a << 8 | b, comes out of GCC as a shift and an OR, and out of Clang as shl edi, 8 and lea eax, [rdi + rsi], an addition.

Two values at once#

OR sets ZF only when both operands are 0, which tests two values with one instruction: both compilers compile a == 0 && b == 0 to or rdi, rsi and sete al, without a branch between the two tests.

All ones#

or rax, -1 sets all 64 bits in 4 bytes, where mov rax, -1 takes 7. But OR reads its destination and writes the flags, and neither vendor’s optimization manual lists it among the idioms whose result does not wait for the register’s old value (Intel’s Section 3.5.1.7, AMD’s Section 2.9.2 for Zen 5); at -O2 both compilers load -1 with the MOV. For XOR of a register with itself both manuals say the opposite.

Atomic OR#

With LOCK and a memory destination, OR sets bits atomically: atomic_fetch_or compiles to lock or when its result is unused and to a CMPXCHG loop when the old value is used. When only one bit of the old value matters, as in atomic_fetch_or(p, 8) & 8, both emit lock bts qword ptr [rdi], 3 (BTS) followed by setc al, which Clang prints as setb al. AOR, from RAO-INT, sets bits atomically but is only weakly ordered with other memory accesses.

Forms

Latency and throughput

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

r = dest | sext(src)             # with LOCK: one atomic read-modify-write;
                                 # an immediate is sign-extended to OSIZE
if not nf:                       # NF=1 (APX) leaves the flags as they were
    of = cf = 0
    sf = msb(r)
    zf = r == 0
    pf = parity(r)
    af = UNDEFINED
dest.write(r)                    # a 32-bit register: bits 63:32 cleared

r = src1 | sext(src2)            # an immediate is sign-extended to OSIZE
if not nf:                       # NF=1 leaves the flags as they were
    of = cf = 0
    sf = msb(r)
    zf = r == 0
    pf = parity(r)
    af = UNDEFINED
dest.write(r)                    # the new destination: bits 63:OSIZE
                                 # cleared, even for 8 and 16 bits

Operands

Flags

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

Legacy forms

none in XED

EVEX forms

APX-EVEX-INT

Attributes

What else XED records about the forms. How to read.

OR m8, imm8 OR m8, r8 OR m16/32/64, imm16/32 OR m16/32/64, imm8 OR m16/32/64, r16/32/64

accepts a LOCK prefix

LOCK forms

locked: atomic read-modify-write; accepts XACQUIRE; accepts XRELEASE

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More General-purpose instructions

• LDS
• LEA
• LEAVE
• LES
• LFS
• LGS
• LODS
• LOOP
• LOOPE
• LOOPNE
• LSS
• MOV
• MOVS
• MOVSX
• MOVSXD
• MOVZX
• MUL
• NEG
• NOP
• NOT
• OUT
• OUTS
• PAUSE
• POP
• POPA
• POPF
• PUSH
• PUSHA
• PUSHF
• RCL
• RCR
• RET
• ROL
• ROR
• SALC
• SAR
• SBB
• SCAS
• SETcc
• SHL

All 109 General-purpose instructions

More APX instructions

• IMUL
• INC
• INVEPT
• INVPCID
• INVVPID
• JMPABS
• KMOVB
• KMOVD
• KMOVQ
• KMOVW
• LDTILECFG
• LZCNT
• MOVBE
• MOVDIR64B
• MOVDIRI
• MOVRS
• MUL
• MULX
• NEG
• NOT
• PDEP
• PEXT
• POP2
• POP2P
• POPCNT
• POPP
• PUSH2
• PUSH2P
• PUSHP
• RCL
• RCR
• RDMSR
• ROL
• ROR
• RORX
• SAR
• SARX
• SBB
• SETcc
• SHL

All 88 APX instructions