ORPD instruction (SSE2)

ORPD is the bitwise OR of two 128-bit values, read as two doubles: ORPS with another name and a 66 prefix, the same bits and no effect on MXCSR. VORPS covers what the operation is for, setting sign bits and combining compares, and VORPD is the VEX and EVEX form. This legacy form ORs into its first operand, leaves bits 128 and up of the register as they were (see SSE and AVX) and needs its memory operand aligned to 16 bytes.

On Zen 5, the recorded orpd xmm8, xmmword ptr [mem] turned -0 OR 7FFFFFFFFFFFFFFFh into FFFFFFFFFFFFFFFFh, the NaN with every bit set, and the register case ORed the denormals 16 and 1 times 2^-1074 into 17 times 2^-1074: no NaN was quieted and no denormal flushed.

In baseline code

In our builds at -O2, with the default target and with -march=x86-64-v2:

copysign(x, y) on doubles is two ANDPD and an ORPD in GCC 14, on scalars and in loops alike, since SSE has no scalar OR; Clang 23 writes the same with ANDPS, ANDNPS and ORPS.
-fabs(b[i]) is one ORPD with -0.0 per element in GCC, which keeps the loop scalar, and ORPS in Clang.
For ((b[i] < c[i]) | (b[i] > d[i])) ? 0.0 : b[i], Clang combines the two CMPLTPD results with ORPD and clears the selected elements with ANDNPD, staying with PD forms next to compares on doubles, as AMD’s Zen 5 guide asks of instructions on the same data (Section 2.11.2). GCC compiles the loop to scalar compares and branches.

Forms

Every encoding of ORPD that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`ORPD xmm, m128` ORPD_XMMxuq_MEMxuq	`66 0F 56 /r`	SSE2
`ORPD xmm, xmm` ORPD_XMMxuq_XMMxuq	`66 0F 56 /r`	SSE2

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Element-wise: each quadword of the result comes from the quadword in the same place in each source.

Result quadword i comes from quadword i of xmm1 and xmm2. Result quadwords 1 to 0: a1|b1, a0|b0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(2):
    xmm1.q[i] = xmm1.q[i] | src2.q[i]
# bits 128 and up of the register are unchanged

Run on AMD Zen 5 (EPYC 9645): 2 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`ORPD xmm, xmm/m128`
`xmm`	explicit	read, write
`xmm/m128`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms: SSE_TYPE_4

Attributes

What else XED records about the forms. How to read.

Memory forms: aligned memory operand

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`SSE2` SSE2	SSE2 `CPUID.01H:EDX[26]` SSE2	Every x86-64 processor in XED’s model and Zen 3 to Zen 6

More SSE2 instructions

All 124 SSE2 instructions

In baseline code#