ORPS instruction (SSE)

ORPS is the bitwise OR of two 128-bit values, read as four singles. Like ANDPS, it sees only bits: MXCSR plays no part, NaNs are not quieted and denormals not flushed. VORPS covers its two uses, setting sign bits and combining compare results, and the VEX and EVEX forms; ORPD is the double name, a byte longer. This legacy form came with the first SSE, writes over its first operand, keeps bits 128 and up of the register (see mixing SSE and AVX) and needs a memory operand aligned to 16 bytes.

On Zen 5, the recorded orps xmm8, xmmword ptr [mem] turned +0 OR -0 into -0 and the denormal 15 times 2^-149 OR 1 into 15 again, and left the NaN 7FFFFFFFh as it was; MXCSR stayed at 1F80h.

In baseline code

In our builds at -O2, with the default target and with -march=x86-64-v2:

Negative absolute values. -fabsf(x) is a single ORPS with -0.0 in Clang 23, on a scalar and in a loop. GCC 14 clears the sign with ANDNPS first and then sets it with ORPS.
Copied signs. copysignf(x, y) ORs the magnitude of x with the sign of y, the last of three logic instructions in both compilers.
Combined compares. For ((b[i] < c[i]) | (b[i] > d[i])) ? 0.0f : b[i], Clang ORs the two CMPLTPS masks with ORPS and clears the selected elements with ANDNPS. GCC ORs them with the integer POR, then uses ANDNPS at the default target and BLENDVPS with x86-64-v2.
Other data. Clang also uses ORPS, a byte shorter than POR, for an integer b[i] | c[i] whose result is only stored, and for _mm_or_si128.

AMD’s Zen 5 guide asks for instructions of one data type on the same data (Section 2.11.2), which Clang’s single-precision ORPS between single-precision compares follows and GCC’s POR does not; its latency spreadsheet gives ORPS one cycle and four per cycle.

Forms

Every encoding of ORPS that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`ORPS xmm, m128` ORPS_XMMxud_MEMxud	`NP 0F 56 /r`	SSE
`ORPS xmm, xmm` ORPS_XMMxud_XMMxud	`NP 0F 56 /r`	SSE

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Element-wise: each doubleword of the result comes from the doubleword in the same place in each source.

Result doubleword i comes from doubleword i of xmm1 and xmm2. Result doublewords 3 to 0: a3|b3, a2|b2, a1|b1, a0|b0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(4):
    xmm1.d[i] = xmm1.d[i] | src2.d[i]
# bits 128 and up of the register are unchanged

Run on AMD Zen 5 (EPYC 9645): 2 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`ORPS xmm, xmm/m128`
`xmm`	explicit	read, write
`xmm/m128`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms: SSE_TYPE_4

Attributes

What else XED records about the forms. How to read.

Memory forms: aligned memory operand

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`SSE` SSE	SSE `CPUID.01H:EDX[25]` SSE	Every x86-64 processor in XED’s model and Zen 3 to Zen 6

More SSE instructions

All 65 SSE instructions

In baseline code#