PABSB

PABSB replaces each byte with its absolute value, treating it as a signed 8-bit integer: 16 results in an XMM register, 8 in an MMX register. SSSE3 added it together with PABSW, PABSD and the related PSIGNB, whose page covers the same SSSE3 and MMX-versus-XMM history. On Zen 5, the recorded pabsb xmm1, xmmword ptr [mem] turned FFh into 01h and 7Fh into itself, and left 80h as 80h: -128 has no positive byte counterpart, so nothing saturates and no flag reports it, the same edge VPABSD’s page describes for doublewords; taken as uint8_t, every result is the correct magnitude.

Without SSSE3#

In our builds at -O2 over fixed-size int8_t arrays, the plain C absolute value compiles to one PABSB per 16 bytes in both GCC 14 and Clang 23 with -march=x86-64-v2. Before SSSE3, both compilers compute abs(x) as the unsigned minimum of x and 0 - x: PXOR to clear a register, PSUBB to negate a copy, and PMINUB between the negated copy and the original. The trick works because negating -128 overflows back to -128, the same value PMINUB then keeps, matching PABSB’s own edge case. This differs from the doubleword form, where the baseline instead flips a sign mask: PMINUD, which the same trick would need, only came with SSE4.1, while PMINUB has existed since SSE.

AMD’s latency spreadsheet for Zen 5 gives PABSB one macro-op with a latency of two cycles, on two of the four vector pipelines; the MMX form has no latency recorded, only a throughput of two.

In the optimization guide

What the optimization guide says about PABSB, a line per claim. Each links to the claim in the guide, with its sources and where they differ.

Skylake to Cooper Lake

• Vectors on all parts: Many MMX instructions, among them the saturating additions and subtractions, comparisons, pmaxsw, pminsw, pavgb and pabsb, run on one port at half Broadwell’s rate.

Forms

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(8):
    mm1.b[i] = abs(src2.sb[i])
# x87: TOP = 0, all tags valid, bits 79:64 of mm1's register all ones

for i in range(16):
    xmm1.b[i] = abs(src2.sb[i])
# bits 128 and up of the register are unchanged

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

PABSB mm, mm/m64

mmx-mem

PABSB xmm, xmm/m128

SSE_TYPE_4

Attributes

What else XED records about the forms. How to read.

PABSB mm, mm/m64

may abort a TSX transaction

PABSB xmm, m128

aligned memory operand

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to PABSB, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More SSSE3 instructions

• PABSD
• PABSW
• PALIGNR
• PHADDD
• PHADDSW
• PHADDW
• PHSUBD
• PHSUBSW
• PHSUBW
• PMADDUBSW
• PMULHRSW
• PSHUFB
• PSIGNB
• PSIGND
• PSIGNW