PABSW

PABSW replaces each word with its absolute value, treating it as a signed 16-bit integer: 8 results in an XMM register, 4 in an MMX register. It came with SSSE3 alongside PABSB, whose page covers the shared MMX-and-XMM history and the related PSIGNB. On Zen 5, the recorded pabsw xmm7, xmmword ptr [mem] turned FFFFh (-1) into 0001h and 7FFFh into itself, and left 8000h as 8000h: -32768 has no positive word counterpart, the same edge that PABSB’s page shows for bytes and VPABSD’s for doublewords.

Without SSSE3#

In our builds at -O2 over fixed-size int16_t arrays, the plain C absolute value compiles to one PABSW per 8 words in both GCC 14 and Clang 23 with -march=x86-64-v2. Before SSSE3, both compilers compute abs(x) as the signed maximum of x and 0 - x: PXOR to clear a register, PSUBW to negate a copy, and PMAXSW between the negated copy and the original. PMAXSW, unlike the unsigned maxima and minima that SSE4.1 added, has existed since SSE, so this trick needs no newer instruction; negating -32768 overflows back to -32768, which the signed maximum then keeps over any positive value, matching PABSW’s edge case.

AMD’s latency spreadsheet for Zen 5 gives PABSW one macro-op with a latency of two cycles, on two of the four vector pipelines; the MMX form has no latency recorded, only a throughput of two.

Forms

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(4):
    mm1.w[i] = abs(src2.sw[i])
# x87: TOP = 0, all tags valid, bits 79:64 of mm1's register all ones

for i in range(8):
    xmm1.w[i] = abs(src2.sw[i])
# bits 128 and up of the register are unchanged

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

PABSW mm, mm/m64

mmx-mem

PABSW xmm, xmm/m128

SSE_TYPE_4

Attributes

What else XED records about the forms. How to read.

PABSW mm, mm/m64

may abort a TSX transaction

PABSW xmm, m128

aligned memory operand

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to PABSW, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More SSSE3 instructions

• PABSB
• PABSD
• PALIGNR
• PHADDD
• PHADDSW
• PHADDW
• PHSUBD
• PHSUBSW
• PHSUBW
• PMADDUBSW
• PMULHRSW
• PSHUFB
• PSIGNB
• PSIGND
• PSIGNW