PACKSSDW instruction (MMX, SSE2)

PACKSSDW narrows signed doublewords to signed words: each is clamped to -32768..32767, and the destination’s doublewords fill the low half of the result, the source’s the high half. In _mm_packs_epi32(a, b), the words from a come first. On Zen 5, packssdw xmm12, xmm12 turned 80000000h (INT_MIN), 7FFFFFFFh (INT_MAX), 55h and 0, in both halves since the two operands were the same register, into 8000h, 7FFFh, 0055h and 0000h, and a case with 0000FFFFh (65535) and 00010000h (65536), both positive but out of range, gave 7FFFh for either. It is MMX’s, extended to XMM registers by SSE2, and like every pack it reads its sources as signed (Intel’s optimization manual, Section 6.4.3). PACKSSWB narrows words to bytes the same way and shows the clamp as a C idiom; PACKUSDW, which SSE4.1 added, clamps doublewords to unsigned words instead.

What this pack does alone

Clang 23 at -O2 compiles the exact C clamp, x < -32768 ? -32768 : x > 32767 ? 32767 : x from int32_t to int16_t, to PACKSSDW alone, one per eight results, at the default target and at -march=x86-64-v2 alike. GCC 14 never reaches for it here: at -march=x86-64-v2 it clamps each element with PMINSD and PMAXSD but stores every word on its own with PEXTRW, and at the default target the whole loop stays scalar. A plain truncating cast, (int16_t)s[i], needs no saturation and uses no pack in either compiler: PUNPCKLQDQ shows the shuffle-based truncation both build instead.

The SSE2 form needs a memory operand aligned to 16 bytes; the MMX form takes two doublewords from each 64-bit operand. AMD’s latency spreadsheet for Zen 5 gives PACKSSDW one macro-op with a latency of two cycles, on pipes FP1 and FP2. VPACKSSDW, the VEX and EVEX form, packs each 128-bit lane on its own, as VPACKUSDW shows.

Forms

Every encoding of PACKSSDW that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`PACKSSDW mm, m64` PACKSSDW_MMXq_MEMq	`NP 0F 6B /r`	MMX
`PACKSSDW mm, mm` PACKSSDW_MMXq_MMXq	`NP 0F 6B /r`	MMX
`PACKSSDW xmm, m128` PACKSSDW_XMMdq_MEMdq	`66 0F 6B /r`	SSE2
`PACKSSDW xmm, xmm` PACKSSDW_XMMdq_XMMdq	`66 0F 6B /r`	SSE2

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Pack: the doublewords of both sources are narrowed to words with saturation; those of xmm1 fill the low half, those of xmm2 the high half.

Result words 7 to 0: b3, b2, b1, b0, a3, a2, a1, a0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

PACKSSDW mm, mm/m64

src1 = mm1.read()  # mm1 as it was
for i in range(4):
    j = i % 2
    if i < 2:
        mm1.w[i] = ssat(src1.sd[j], 16)
    else:
        mm1.w[i] = ssat(src2.sd[j], 16)
# x87: TOP = 0, all tags valid, bits 79:64 of mm1's register all ones

Run on AMD Zen 5 (EPYC 9645): 2 cases.

PACKSSDW xmm, xmm/m128

src1 = xmm1.read()  # xmm1 as it was
for i in range(8):
    j = i % 4
    if i < 4:
        xmm1.w[i] = ssat(src1.sd[j], 16)
    else:
        xmm1.w[i] = ssat(src2.sd[j], 16)
# bits 128 and up of the register are unchanged

Run on AMD Zen 5 (EPYC 9645): 2 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`PACKSSDW mm, mm/m64`
`mm`	explicit	read, write
`mm/m64`	explicit	read
`PACKSSDW xmm, xmm/m128`
`xmm`	explicit	read, write
`xmm/m128`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

PACKSSDW mm, m64: mmx-mem
PACKSSDW mm, mm: none in XED
PACKSSDW xmm, xmm/m128: SSE_TYPE_4

Attributes

What else XED records about the forms. How to read.

PACKSSDW mm, mm/m64: may abort a TSX transaction
PACKSSDW xmm, m128: aligned memory operand

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to PACKSSDW, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`_mm_packs_epi32` `__m128i _mm_packs_epi32(__m128i __a, __m128i __b)`	`PACKSSDW xmm, xmm` Legacy -msse2

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`PENTIUMMMX` MMX	MMX `CPUID.01H:EDX[23]` MMX	Every x86-64 processor in XED’s model and Zen 3 to Zen 6
`SSE2` SSE2	SSE2 `CPUID.01H:EDX[26]` SSE2	Every x86-64 processor in XED’s model and Zen 3 to Zen 6

More MMX instructions

All 47 MMX instructions

More SSE2 instructions

All 124 SSE2 instructions

What this pack does alone#