PACKSSWB instruction (MMX, SSE2)

PACKSSWB narrows signed words to signed bytes: each word is clamped to -128..127, and the destination’s words fill the low half of the result, the source’s the high half. In _mm_packs_epi16(a, b), the bytes from a come first. On Zen 5, packsswb xmm12, xmmword ptr [mem] turned FFFFh into FFh, 0080h, 00FFh and 0100h into 7Fh, and FF80h and FF7Fh into 80h, and kept bits 511:128 of ZMM12. It is MMX’s, extended to XMM registers by SSE2, and like every pack it reads its sources as signed (Intel’s optimization manual, Section 6.4.3). PACKUSWB, which clamps to 0..255, describes the packs’ use after widened arithmetic.

Clamping, and masks

The clamp is the C idiom x < -128 ? -128 : x > 127 ? 127 : x from int16_t to int8_t. In our builds at -O2 for the SSE2 baseline and for x86-64-v2:

Clang 23 compiles it to PACKSSWB alone, one per 16 results. GCC 14 clamps first with PMINSW and PMAXSW, clears the high bytes with PAND and packs with PACKUSWB, the same steps as for a plain truncation (int8_t)s[i], which packs cannot do alone.
Word compares give 0000h or FFFFh per element, and saturation keeps those as 00h and FFh. For d[i] = a[i] < b[i] ? -1 : 0 with int16_t sources and int8_t results, Clang packs the PCMPGTW results with PACKSSWB; GCC turns them into 0 or 1, packs with PACKUSWB and negates with PSUBB from zero.

The MMX form packs four words of each operand into eight bytes; the SSE2 form needs a memory operand aligned to 16 bytes. AMD’s latency spreadsheet for Zen 5 gives PACKSSWB one macro-op with a latency of two cycles, on pipes FP1 and FP2. PACKSSDW narrows doublewords to signed words, PMOVSXBW widens bytes back, and VPACKSSWB, the VEX and EVEX form, packs each 128-bit lane on its own, as VPACKUSWB shows.

Forms

Every encoding of PACKSSWB that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`PACKSSWB mm, m64` PACKSSWB_MMXq_MEMq	`NP 0F 63 /r`	MMX
`PACKSSWB mm, mm` PACKSSWB_MMXq_MMXq	`NP 0F 63 /r`	MMX
`PACKSSWB xmm, m128` PACKSSWB_XMMdq_MEMdq	`66 0F 63 /r`	SSE2
`PACKSSWB xmm, xmm` PACKSSWB_XMMdq_XMMdq	`66 0F 63 /r`	SSE2

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Pack: the words of both sources are narrowed to bytes with saturation; those of xmm1 fill the low half, those of xmm2 the high half.

Result bytes 15 to 0: b7, b6, b5, b4, b3, b2, b1, b0, a7, a6, a5, a4, a3, a2, a1, a0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

PACKSSWB mm, mm/m64

src1 = mm1.read()  # mm1 as it was
for i in range(8):
    j = i % 4
    if i < 4:
        mm1.b[i] = ssat(src1.sw[j], 8)
    else:
        mm1.b[i] = ssat(src2.sw[j], 8)
# x87: TOP = 0, all tags valid, bits 79:64 of mm1's register all ones

Run on AMD Zen 5 (EPYC 9645): 2 cases.

PACKSSWB xmm, xmm/m128

src1 = xmm1.read()  # xmm1 as it was
for i in range(16):
    j = i % 8
    if i < 8:
        xmm1.b[i] = ssat(src1.sw[j], 8)
    else:
        xmm1.b[i] = ssat(src2.sw[j], 8)
# bits 128 and up of the register are unchanged

Run on AMD Zen 5 (EPYC 9645): 2 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`PACKSSWB mm, mm/m64`
`mm`	explicit	read, write
`mm/m64`	explicit	read
`PACKSSWB xmm, xmm/m128`
`xmm`	explicit	read, write
`xmm/m128`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

PACKSSWB mm, m64: mmx-mem
PACKSSWB mm, mm: none in XED
PACKSSWB xmm, xmm/m128: SSE_TYPE_4

Attributes

What else XED records about the forms. How to read.

PACKSSWB mm, mm/m64: may abort a TSX transaction
PACKSSWB xmm, m128: aligned memory operand

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to PACKSSWB, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`_mm_packs_epi16` `__m128i _mm_packs_epi16(__m128i __a, __m128i __b)`	`PACKSSWB xmm, xmm` Legacy -msse2

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`PENTIUMMMX` MMX	MMX `CPUID.01H:EDX[23]` MMX	Every x86-64 processor in XED’s model and Zen 3 to Zen 6
`SSE2` SSE2	SSE2 `CPUID.01H:EDX[26]` SSE2	Every x86-64 processor in XED’s model and Zen 3 to Zen 6

More MMX instructions

All 47 MMX instructions

More SSE2 instructions

All 124 SSE2 instructions

Clamping, and masks#