PADDB instruction (MMX, SSE2)

PADDB adds bytes element by element and keeps the low eight bits of each sum, so the result wraps around, the same for signed and unsigned bytes: 16 in an XMM register, 8 in an MMX register. PADDD covers what the family’s legacy forms share, from the PCMPEQD all-ones constant to the MMX register state. On Zen 5, the recorded paddb xmm12, xmm6 turned 7Fh plus 01h into 80h (127 plus 1 wrapping to -128) and 80h plus 80h into 00h, and left bits 255:128 of the register as they were (see mixing SSE and AVX). The additions that clamp instead of wrapping are PADDSB for signed bytes and PADDUSB for unsigned ones.

Bytes in compiled code

In our builds at -O2 for the x86-64 baseline, over arrays of 1,024 bytes:

Sums. a[i] = b[i] + c[i] over uint8_t or int8_t is one PADDB per 16 bytes in GCC 14 and Clang 23, with both operands loaded by MOVDQU and an unaligned store.
Constants. b[i] + 7 adds a register holding 7 in every byte, which GCC builds with MOVD and PSHUFD and Clang loads ready-made from memory.
Negation. There is no negate instruction, and PADDB plays no part in it: -b[i] is a PSUBB of the value from a register zeroed with PXOR, in both compilers, the trick PSUBB’s page describes.

AMD’s latency spreadsheet for Zen 5 gives PADDB one cycle, four per cycle, on all four vector pipes. The MMX form came with MMX and the XMM form with SSE2, whose memory operand must be aligned to 16 bytes. VPADDB is the VEX and EVEX form; PADDW and PADDQ take wider elements.

Forms

Every encoding of PADDB that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`PADDB mm, m64` PADDB_MMXq_MEMq	`NP 0F FC /r`	MMX
`PADDB mm, mm` PADDB_MMXq_MMXq	`NP 0F FC /r`	MMX
`PADDB xmm, m128` PADDB_XMMdq_MEMdq	`66 0F FC /r`	SSE2
`PADDB xmm, xmm` PADDB_XMMdq_XMMdq	`66 0F FC /r`	SSE2

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Element-wise: each byte of the result comes from the byte in the same place in each source.

Shown: bytes 7 to 0. Every byte works alike: 8 and 16 bytes in the mm and xmm forms.

Result byte i comes from byte i of xmm1 and xmm2. Result bytes 7 to 0: a7+b7, a6+b6, a5+b5, a4+b4, a3+b3, a2+b2, a1+b1, a0+b0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

PADDB mm, mm/m64

for i in range(8):
    mm1.b[i] = mm1.b[i] + src2.b[i]
# x87: TOP = 0, all tags valid, bits 79:64 of mm1's register all ones

Run on AMD Zen 5 (EPYC 9645): 2 cases.

PADDB xmm, xmm/m128

for i in range(16):
    xmm1.b[i] = xmm1.b[i] + src2.b[i]
# bits 128 and up of the register are unchanged

Run on AMD Zen 5 (EPYC 9645): 2 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`PADDB mm, mm/m64`
`mm`	explicit	read, write
`mm/m64`	explicit	read
`PADDB xmm, xmm/m128`
`xmm`	explicit	read, write
`xmm/m128`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

PADDB mm, mm/m64: mmx-mem
PADDB xmm, xmm/m128: SSE_TYPE_4

Attributes

What else XED records about the forms. How to read.

PADDB mm, mm/m64: may abort a TSX transaction
PADDB xmm, m128: aligned memory operand

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to PADDB, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`_mm_add_epi8` `__m128i _mm_add_epi8(__m128i __a, __m128i __b)`	`PADDB xmm, xmm` Legacy -msse2
`_mm_add_pi8` `__m64 _mm_add_pi8(__m64 __m1, __m64 __m2)`	`PADDB xmm, xmm` Legacy -msse2

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`PENTIUMMMX` MMX	MMX `CPUID.01H:EDX[23]` MMX	Every x86-64 processor in XED’s model and Zen 3 to Zen 6
`SSE2` SSE2	SSE2 `CPUID.01H:EDX[26]` SSE2	Every x86-64 processor in XED’s model and Zen 3 to Zen 6

More MMX instructions

All 47 MMX instructions

More SSE2 instructions

All 124 SSE2 instructions

Bytes in compiled code#