PADDD instruction (MMX, SSE2)

PADDD adds doublewords element by element and keeps the low 32 bits of each sum, so overflow wraps around, the same for signed and unsigned numbers. Unlike ADD, it sets no flags and nothing records that a sum overflowed. Saturating additions exist only for bytes and words: PADDSB and PADDSW for signed elements, PADDUSB and PADDUSW for unsigned ones.

In compiled code

Vectorized integer loops are where PADDD comes from. GCC 14 and Clang 23 at -O2 compile a[i] = b[i] + c[i] over ints to MOVDQU loads, PADDD and an unaligned store. A sum of the elements vectorizes too, unlike a sum of floats (see ADDPS), because wrapping integer addition gives the same total in any order: the loop keeps four partial sums in a register, one per element, and adds them together at the end with shifts or shuffles and two more PADDDs.

A constant of all ones needs no memory: pcmpeqd xmm0, xmm0 sets every bit, and AMD’s guide for Zen 5 lists it among the idioms that do not wait for the register’s old value (Section 2.9.2). All ones is -1 in every element, so both compilers subtract 1 with PADDD of it, and Clang 23 also adds 1 by subtracting it with PSUBD instead of building a vector of ones with MOVD and PSHUFD, as GCC 14 does.

SSE2, MMX and VEX

The legacy SSE2 form needs a memory operand aligned to 16 bytes, so compilers load unaligned data with MOVDQU first.
The MMX form adds two doublewords of an MMX register. Like every MMX instruction it puts the x87 unit in MMX state, and EMMS must follow before x87 code runs.
VPADDD is the VEX form for 128 and 256 bits and the EVEX form with masking and a broadcast doubleword.

PADDB, PADDW and PADDQ do the same for other element sizes.

Forms

Every encoding of PADDD that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`PADDD mm, m64` PADDD_MMXq_MEMq	`NP 0F FE /r`	MMX
`PADDD mm, mm` PADDD_MMXq_MMXq	`NP 0F FE /r`	MMX
`PADDD xmm, m128` PADDD_XMMdq_MEMdq	`66 0F FE /r`	SSE2
`PADDD xmm, xmm` PADDD_XMMdq_XMMdq	`66 0F FE /r`	SSE2

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Element-wise: each doubleword of the result comes from the doubleword in the same place in each source.

Every doubleword works alike: 2 and 4 doublewords in the mm and xmm forms.

Result doubleword i comes from doubleword i of xmm1 and xmm2. Result doublewords 3 to 0: a3+b3, a2+b2, a1+b1, a0+b0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

PADDD mm, mm/m64

for i in range(2):
    mm1.d[i] = mm1.d[i] + src2.d[i]
# x87: TOP = 0, all tags valid, bits 79:64 of mm1's register all ones

Run on AMD Zen 5 (EPYC 9645): 2 cases.

PADDD xmm, xmm/m128

for i in range(4):
    xmm1.d[i] = xmm1.d[i] + src2.d[i]
# bits 128 and up of the register are unchanged

Run on AMD Zen 5 (EPYC 9645): 2 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`PADDD mm, mm/m64`
`mm`	explicit	read, write
`mm/m64`	explicit	read
`PADDD xmm, xmm/m128`
`xmm`	explicit	read, write
`xmm/m128`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

PADDD mm, mm/m64: mmx-mem
PADDD xmm, xmm/m128: SSE_TYPE_4

Attributes

What else XED records about the forms. How to read.

PADDD mm, mm/m64: may abort a TSX transaction
PADDD xmm, m128: aligned memory operand

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to PADDD, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`_mm_add_epi32` `__m128i _mm_add_epi32(__m128i __a, __m128i __b)`	`PADDD xmm, xmm` Legacy -msse2
`_mm_add_pi32` `__m64 _mm_add_pi32(__m64 __m1, __m64 __m2)`	`PADDD xmm, xmm` Legacy -msse2

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`PENTIUMMMX` MMX	MMX `CPUID.01H:EDX[23]` MMX	Every x86-64 processor in XED’s model and Zen 3 to Zen 6
`SSE2` SSE2	SSE2 `CPUID.01H:EDX[26]` SSE2	Every x86-64 processor in XED’s model and Zen 3 to Zen 6

More MMX instructions

All 47 MMX instructions

More SSE2 instructions

All 124 SSE2 instructions

In compiled code#

SSE2, MMX and VEX#