PADDQ instruction (SSE2)

PADDQ adds quadwords and keeps the low 64 bits of each sum, the same for signed and unsigned numbers: two in an XMM register, one in an MMX register. PADDB covers what the family’s legacy forms share. On Zen 5, the recorded paddq xmm0, xmm13 turned FFFFFFFFFFFFFFFFh plus FFFFFFFFFFFFFFFFh into FFFFFFFFFFFFFFFEh (-1 plus -1) and 7FFFFFFFFFFFFFFFh plus 0000000000000001h into 8000000000000000h (the largest int64_t plus 1, wrapping to the smallest), leaving bits 255:128 of the register as they were (see mixing SSE and AVX). Unlike ADD, it sets no flags, so an overflow goes unrecorded. There is no saturating quadword addition: SSE’s saturating arithmetic covers only bytes and words. Intel’s optimization manual covers PADDQ and its subtraction together as “packed 64-bit add/subtract” (Section 6.6.13).

Quadwords in compiled code

int64_t, uint64_t and pointer sums at -O2 are one PADDQ per two quadwords, both operands loaded by MOVDQU, in GCC 14 and Clang 23. Adding the same scalar offset to every element of an array (b[i] + off) broadcasts the scalar into both lanes of a register first, with PUNPCKLQDQ in GCC and PSHUFD in Clang, and then adds with PADDQ from that one register for the whole array.

The MMX encoding of PADDQ came with SSE2, not with MMX, which had no quadword arithmetic; PSUBQ notes the same for subtraction. AMD’s latency spreadsheet for Zen 5 gives PADDQ one cycle, four per cycle, on all four vector pipes. A memory operand of the XMM form must be aligned to 16 bytes. VPADDQ is the VEX and EVEX form, the latter with masking and a broadcast quadword.

In the optimization guide

What the optimization guide says about PADDQ, a line per claim. Each links to the claim in the guide, with its sources and where they differ.

Silvermont to Goldmont Plus

Vectors and cryptography: pshufb, pmulld, paddq and psubq are slow on Silvermont and much faster from Goldmont on.

Forms

Every encoding of PADDQ that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`PADDQ mm, m64` PADDQ_MMXq_MEMq	`NP 0F D4 /r`	SSE2 + MMX
`PADDQ mm, mm` PADDQ_MMXq_MMXq	`NP 0F D4 /r`	SSE2 + MMX
`PADDQ xmm, m128` PADDQ_XMMdq_MEMdq	`66 0F D4 /r`	SSE2
`PADDQ xmm, xmm` PADDQ_XMMdq_XMMdq	`66 0F D4 /r`	SSE2

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Element-wise: each quadword of the result comes from the quadword in the same place in each source.

Every quadword works alike: 1 and 2 quadwords in the mm and xmm forms.

Result quadword i comes from quadword i of xmm1 and xmm2. Result quadwords 1 to 0: a1+b1, a0+b0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

PADDQ mm, mm/m64

i = 0
mm1.q[i] = mm1.q[i] + src2.q[i]
# x87: TOP = 0, all tags valid, bits 79:64 of mm1's register all ones

Run on AMD Zen 5 (EPYC 9645): 2 cases.

PADDQ xmm, xmm/m128

for i in range(2):
    xmm1.q[i] = xmm1.q[i] + src2.q[i]
# bits 128 and up of the register are unchanged

Run on AMD Zen 5 (EPYC 9645): 2 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`PADDQ mm, mm/m64`
`mm`	explicit	read, write
`mm/m64`	explicit	read
`PADDQ xmm, xmm/m128`
`xmm`	explicit	read, write
`xmm/m128`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

PADDQ mm, mm/m64: mmx-mem
PADDQ xmm, xmm/m128: SSE_TYPE_4

Attributes

What else XED records about the forms. How to read.

PADDQ mm, mm/m64: may abort a TSX transaction
PADDQ xmm, m128: aligned memory operand

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to PADDQ, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`_mm_add_epi64` `__m128i _mm_add_epi64(__m128i __a, __m128i __b)`	`PADDQ xmm, xmm` Legacy -msse2

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`SSE2MMX` SSE2	SSE2 + MMX `CPUID.01H:EDX[26]` SSE2 `CPUID.01H:EDX[23]` MMX	Every x86-64 processor in XED’s model and Zen 3 to Zen 6
`SSE2` SSE2	SSE2 `CPUID.01H:EDX[26]` SSE2	Every x86-64 processor in XED’s model and Zen 3 to Zen 6

More SSE2 instructions

All 124 SSE2 instructions

Quadwords in compiled code#