PADDSB instruction (MMX, SSE2)

PADDSB adds bytes as signed numbers and clamps each sum to the range of a byte instead of letting it wrap: a sum above 127 becomes 7Fh and one below -128 becomes 80h, and nothing records that it happened. On Zen 5, the recorded paddsb xmm8, xmm15 turned 7Fh plus 01h into 7Fh, where PADDB gives 80h, both 80h plus FFh and 80h plus 80h into 80h, and FFh plus FFh into FEh (-1 plus -1), and left bits 255:128 of the register as they were (see mixing SSE and AVX). Its partners are PADDSW for words, PSUBSB for the subtraction and PADDUSB for unsigned bytes; SSE has saturating arithmetic for bytes and words only.

Writing it in C

C has no saturating addition, so a loop spells out the clamp, as in int s = b[i] + c[i]; a[i] = s > 127 ? 127 : s < -128 ? -128 : s; over int8_t. In our builds at -O2 for the x86-64 baseline:

Clang 23 recognizes the pattern and emits one PADDSB per 16 bytes, with the second operand from memory. It does the same when the loop tests __builtin_add_overflow and picks 7Fh or 80h by the sign.
GCC 14 follows the source: it widens both inputs to words, with signs made by PCMPGTB against zero and interleaved by PUNPCKLBW and PUNPCKHBW, adds with PADDW, clamps with PMAXSW against FF80h and PMINSW against 007Fh, keeps the low byte of each word with PAND and packs them with PACKUSWB: 19 vector instructions per 16 bytes, copies included. With -march=x86-64-v2 it widens with PMOVSXBW instead. The __builtin_add_overflow loop stays scalar.

_mm_adds_epi8 is PADDSB in both compilers, and Clang compiles the MMX intrinsic _mm_adds_pi8 to the XMM form too.

AMD’s latency spreadsheet for Zen 5 gives PADDSB two cycles and two per cycle, on pipes FP0 and FP3, where PADDB takes one cycle at four per cycle. Intel’s optimization manual counts the MMX form among those that Skylake runs at half the throughput of earlier cores (Section 15.16.5). The MMX form came with MMX and the XMM form with SSE2, whose memory operand must be aligned to 16 bytes. VPADDSB is the VEX and EVEX form.

Forms

Every encoding of PADDSB that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`PADDSB mm, m64` PADDSB_MMXq_MEMq	`NP 0F EC /r`	MMX
`PADDSB mm, mm` PADDSB_MMXq_MMXq	`NP 0F EC /r`	MMX
`PADDSB xmm, m128` PADDSB_XMMdq_MEMdq	`66 0F EC /r`	SSE2
`PADDSB xmm, xmm` PADDSB_XMMdq_XMMdq	`66 0F EC /r`	SSE2

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Element-wise: each byte of the result comes from the byte in the same place in each source.

Shown: bytes 7 to 0. Every byte works alike: 8 and 16 bytes in the mm and xmm forms.

Result byte i comes from byte i of xmm1 and xmm2. Result bytes 7 to 0: a7+b7, a6+b6, a5+b5, a4+b4, a3+b3, a2+b2, a1+b1, a0+b0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

PADDSB mm, mm/m64

for i in range(8):
    sa = mm1.sb[i]
    sb = src2.sb[i]
    mm1.b[i] = ssat(sa + sb, 8)
# x87: TOP = 0, all tags valid, bits 79:64 of mm1's register all ones

Run on AMD Zen 5 (EPYC 9645): 2 cases.

PADDSB xmm, xmm/m128

for i in range(16):
    sa = xmm1.sb[i]
    sb = src2.sb[i]
    xmm1.b[i] = ssat(sa + sb, 8)
# bits 128 and up of the register are unchanged

Run on AMD Zen 5 (EPYC 9645): 2 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`PADDSB mm, mm/m64`
`mm`	explicit	read, write
`mm/m64`	explicit	read
`PADDSB xmm, xmm/m128`
`xmm`	explicit	read, write
`xmm/m128`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

PADDSB mm, mm/m64: mmx-mem
PADDSB xmm, xmm/m128: SSE_TYPE_4

Attributes

What else XED records about the forms. How to read.

PADDSB mm, mm/m64: may abort a TSX transaction
PADDSB xmm, m128: aligned memory operand

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to PADDSB, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`_mm_adds_epi8` `__m128i _mm_adds_epi8(__m128i __a, __m128i __b)`	`PADDSB xmm, xmm` Legacy -msse2
`_mm_adds_pi8` `__m64 _mm_adds_pi8(__m64 __m1, __m64 __m2)`	`PADDSB xmm, xmm` Legacy -msse2

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`PENTIUMMMX` MMX	MMX `CPUID.01H:EDX[23]` MMX	Every x86-64 processor in XED’s model and Zen 3 to Zen 6
`SSE2` SSE2	SSE2 `CPUID.01H:EDX[26]` SSE2	Every x86-64 processor in XED’s model and Zen 3 to Zen 6

More MMX instructions

All 47 MMX instructions

More SSE2 instructions

All 124 SSE2 instructions

Writing it in C#