PADDSW instruction (MMX, SSE2)

PADDSW adds words as signed numbers and clamps each sum to the range of a word instead of letting it wrap: a sum above 32767 becomes 7FFFh and one below -32768 becomes 8000h, with nothing recorded. On Zen 5, the recorded paddsw xmm12, xmm6 turned 7FFFh plus 0001h into 7FFFh, where PADDW gives 8000h, and FFFFh plus FFFFh into FFFEh (-1 plus -1, still in range), leaving bits 255:128 of the register as they were (see mixing SSE and AVX). PADDSB covers what the saturating family shares (the clamp, PADDUSB and PSUBSB, and the _mm_adds_pi8/_mm_adds_epi8 intrinsics); its partners here are PSUBSW for the subtraction and PADDUSW for unsigned words.

In compiled code

In our builds at -O2 for the x86-64 baseline, over int16_t arrays:

The explicit clamp. int32_t s = b[i] + c[i]; a[i] = s > 32767 ? 32767 : s < -32768 ? -32768 : s; and the equivalent test with __builtin_add_overflow both compile to one PADDSW per 8 words in Clang 23, with the second operand loaded by MOVDQU. GCC 14 recognizes neither: it widens each word to a doubleword with PCMPGTW and PUNPCKLWD/PUNPCKHWD, adds with PADDD, and clamps with doubleword compares and blends instead of PMAXSD/PMINSD, since the baseline has no SSE4.1; the __builtin_add_overflow form stays scalar in GCC.
The intrinsic. _mm_adds_epi16 is PADDSW in both compilers, with the second operand from memory in GCC.

AMD’s latency spreadsheet for Zen 5 gives PADDSW two cycles, two per cycle, on pipes FP0 and FP3, where PADDW takes one cycle at four per cycle. Intel’s optimization manual counts the MMX form among those that Skylake runs at half the throughput of earlier cores (Section 15.16.5). The MMX form came with MMX and the XMM form with SSE2, whose memory operand must be aligned to 16 bytes. VPADDSW is the VEX and EVEX form.

Forms

Every encoding of PADDSW that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`PADDSW mm, m64` PADDSW_MMXq_MEMq	`NP 0F ED /r`	MMX
`PADDSW mm, mm` PADDSW_MMXq_MMXq	`NP 0F ED /r`	MMX
`PADDSW xmm, m128` PADDSW_XMMdq_MEMdq	`66 0F ED /r`	SSE2
`PADDSW xmm, xmm` PADDSW_XMMdq_XMMdq	`66 0F ED /r`	SSE2

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Element-wise: each word of the result comes from the word in the same place in each source.

Every word works alike: 4 and 8 words in the mm and xmm forms.

Result word i comes from word i of xmm1 and xmm2. Result words 7 to 0: a7+b7, a6+b6, a5+b5, a4+b4, a3+b3, a2+b2, a1+b1, a0+b0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

PADDSW mm, mm/m64

for i in range(4):
    sa = mm1.sw[i]
    sb = src2.sw[i]
    mm1.w[i] = ssat(sa + sb, 16)
# x87: TOP = 0, all tags valid, bits 79:64 of mm1's register all ones

Run on AMD Zen 5 (EPYC 9645): 2 cases.

PADDSW xmm, xmm/m128

for i in range(8):
    sa = xmm1.sw[i]
    sb = src2.sw[i]
    xmm1.w[i] = ssat(sa + sb, 16)
# bits 128 and up of the register are unchanged

Run on AMD Zen 5 (EPYC 9645): 2 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`PADDSW mm, mm/m64`
`mm`	explicit	read, write
`mm/m64`	explicit	read
`PADDSW xmm, xmm/m128`
`xmm`	explicit	read, write
`xmm/m128`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

PADDSW mm, mm/m64: mmx-mem
PADDSW xmm, xmm/m128: SSE_TYPE_4

Attributes

What else XED records about the forms. How to read.

PADDSW mm, mm/m64: may abort a TSX transaction
PADDSW xmm, m128: aligned memory operand

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to PADDSW, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`_mm_adds_epi16` `__m128i _mm_adds_epi16(__m128i __a, __m128i __b)`	`PADDSW xmm, xmm` Legacy -msse2
`_mm_adds_pi16` `__m64 _mm_adds_pi16(__m64 __m1, __m64 __m2)`	`PADDSW xmm, xmm` Legacy -msse2

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`PENTIUMMMX` MMX	MMX `CPUID.01H:EDX[23]` MMX	Every x86-64 processor in XED’s model and Zen 3 to Zen 6
`SSE2` SSE2	SSE2 `CPUID.01H:EDX[26]` SSE2	Every x86-64 processor in XED’s model and Zen 3 to Zen 6

More MMX instructions

All 47 MMX instructions

More SSE2 instructions

All 124 SSE2 instructions

In compiled code#