PADDUSB instruction (MMX, SSE2)

PADDUSB adds bytes as unsigned numbers and clamps each sum at FFh: a sum above 255 becomes 255 instead of wrapping around. It is the operation of choice for pixels and other 8-bit intensities, where brightening a nearly white pixel should give white, not black. On Zen 5, the recorded paddusb xmm8, xmm15 turned 80h plus 80h and 01h plus FFh into FFh, where PADDB gives 00h, and 7Fh plus 7Fh into FEh, a sum that the signed PADDSB clamps to 7Fh; bits 255:128 of the register kept their value (see mixing SSE and AVX). PADDSB’s page describes how compilers treat saturating arithmetic written in C. PADDUSW is the word form, and PSUBUSB subtracts down to zero.

In compiled code

In our builds at -O2 for the x86-64 baseline, over uint8_t arrays:

Clang 23 turns each way of writing the clamp into one PADDUSB per 16 bytes: s > 255 ? 255 : s with s an int sum, the wrapped sum tested for a carry, s < b[i] ? 255 : s, and brightening by a constant, b[i] + 40 clamped, with a vector of 28h.
GCC 14 follows the source. For the int sum it widens the bytes to words with PUNPCKLBW and PUNPCKHBW against zero, adds with PADDW, clamps to 255 with a PSUBUSW, PCMPEQW and a select, and packs with PACKUSWB; with -march=x86-64-v2 the clamp is one PMINUW. For the carry test it adds with PADDB, finds the carries with PSUBUSB and PCMPEQB, and selects FFh there, with PBLENDVB at -v2.

Intel’s optimization manual clips unsigned words to any range [low, high] with a saturating addition that pins the top, a saturating subtraction that pins the bottom and a plain addition to undo the offsets, a method limited to bytes and words, the two sizes with unsigned saturation (Section 6.6.6.2).

AMD’s latency spreadsheet for Zen 5 gives PADDUSB two cycles and two per cycle, on pipes FP0 and FP3, where PADDB takes one cycle at four per cycle; Intel’s manual counts the MMX form among those that Skylake runs at half the throughput of earlier cores (Section 15.16.5). The MMX form came with MMX and the XMM form with SSE2, whose memory operand must be aligned to 16 bytes. VPADDUSB is the VEX and EVEX form.

Forms

Every encoding of PADDUSB that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`PADDUSB mm, m64` PADDUSB_MMXq_MEMq	`NP 0F DC /r`	MMX
`PADDUSB mm, mm` PADDUSB_MMXq_MMXq	`NP 0F DC /r`	MMX
`PADDUSB xmm, m128` PADDUSB_XMMdq_MEMdq	`66 0F DC /r`	SSE2
`PADDUSB xmm, xmm` PADDUSB_XMMdq_XMMdq	`66 0F DC /r`	SSE2

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Element-wise: each byte of the result comes from the byte in the same place in each source.

Shown: bytes 7 to 0. Every byte works alike: 8 and 16 bytes in the mm and xmm forms.

Result byte i comes from byte i of xmm1 and xmm2. Result bytes 7 to 0: a7+b7, a6+b6, a5+b5, a4+b4, a3+b3, a2+b2, a1+b1, a0+b0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

PADDUSB mm, mm/m64

for i in range(8):
    mm1.b[i] = usat(mm1.b[i] + src2.b[i], 8)
# x87: TOP = 0, all tags valid, bits 79:64 of mm1's register all ones

Run on AMD Zen 5 (EPYC 9645): 2 cases.

PADDUSB xmm, xmm/m128

for i in range(16):
    a = xmm1.b[i]
    b = src2.b[i]
    xmm1.b[i] = usat(a + b, 8)
# bits 128 and up of the register are unchanged

Run on AMD Zen 5 (EPYC 9645): 2 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`PADDUSB mm, mm/m64`
`mm`	explicit	read, write
`mm/m64`	explicit	read
`PADDUSB xmm, xmm/m128`
`xmm`	explicit	read, write
`xmm/m128`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

PADDUSB mm, m64: mmx-mem
PADDUSB mm, mm: none in XED
PADDUSB xmm, xmm/m128: SSE_TYPE_4

Attributes

What else XED records about the forms. How to read.

PADDUSB mm, mm/m64: may abort a TSX transaction
PADDUSB xmm, m128: aligned memory operand

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to PADDUSB, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`_mm_adds_epu8` `__m128i _mm_adds_epu8(__m128i __a, __m128i __b)`	`PADDUSB xmm, xmm` Legacy -msse2
`_mm_adds_pu8` `__m64 _mm_adds_pu8(__m64 __m1, __m64 __m2)`	`PADDUSB xmm, xmm` Legacy -msse2

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`PENTIUMMMX` MMX	MMX `CPUID.01H:EDX[23]` MMX	Every x86-64 processor in XED’s model and Zen 3 to Zen 6
`SSE2` SSE2	SSE2 `CPUID.01H:EDX[26]` SSE2	Every x86-64 processor in XED’s model and Zen 3 to Zen 6

More MMX instructions

All 47 MMX instructions

More SSE2 instructions

All 124 SSE2 instructions

In compiled code#