PADDUSW instruction (MMX, SSE2)

PADDUSW adds words as unsigned numbers and clamps each sum to FFFFh instead of letting it wrap. On Zen 5, the recorded paddusw xmm1, xmm2 turned FFFFh (65535) plus 0001h into FFFFh, where PADDW gives 0000h, and 8000h plus 8000h (32768 plus 32768) into FFFFh as well, leaving bits 255:128 of the register as they were (see mixing SSE and AVX). PADDUSB covers what the saturating family shares; its partners here are PADDSW for signed words and PSUBUSW for the subtraction.

In compiled code

In our builds at -O2 for the x86-64 baseline, over uint16_t arrays:

Clamped sums. uint32_t s = (uint32_t)b[i] + c[i]; a[i] = s > 65535 ? 65535 : s;, against both another array and a constant (1000), compiles to one PADDUSW per 8 words in Clang 23, the second case with the constant broadcast into a register ahead of the loop. GCC 14 recognizes neither: like the signed case on PADDSW’s page, it widens to doublewords, adds, and clamps with compares and blends rather than emitting PADDUSW.

AMD’s latency spreadsheet for Zen 5 gives PADDUSW two cycles, two per cycle, on pipes FP0 and FP3, where PADDW takes one cycle at four per cycle. Intel’s optimization manual counts the MMX form among those that Skylake runs at half the throughput of earlier cores (Section 15.16.5). The MMX form came with MMX and the XMM form with SSE2, whose memory operand must be aligned to 16 bytes. VPADDUSW is the VEX and EVEX form.

Forms

Every encoding of PADDUSW that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`PADDUSW mm, m64` PADDUSW_MMXq_MEMq	`NP 0F DD /r`	MMX
`PADDUSW mm, mm` PADDUSW_MMXq_MMXq	`NP 0F DD /r`	MMX
`PADDUSW xmm, m128` PADDUSW_XMMdq_MEMdq	`66 0F DD /r`	SSE2
`PADDUSW xmm, xmm` PADDUSW_XMMdq_XMMdq	`66 0F DD /r`	SSE2

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Element-wise: each word of the result comes from the word in the same place in each source.

Every word works alike: 4 and 8 words in the mm and xmm forms.

Result word i comes from word i of xmm1 and xmm2. Result words 7 to 0: a7+b7, a6+b6, a5+b5, a4+b4, a3+b3, a2+b2, a1+b1, a0+b0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

PADDUSW mm, mm/m64

for i in range(4):
    a = mm1.w[i]
    b = src2.w[i]
    mm1.w[i] = usat(a + b, 16)
# x87: TOP = 0, all tags valid, bits 79:64 of mm1's register all ones

Run on AMD Zen 5 (EPYC 9645): 2 cases.

PADDUSW xmm, xmm/m128

for i in range(8):
    a = xmm1.w[i]
    b = src2.w[i]
    xmm1.w[i] = usat(a + b, 16)
# bits 128 and up of the register are unchanged

Run on AMD Zen 5 (EPYC 9645): 2 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`PADDUSW mm, mm/m64`
`mm`	explicit	read, write
`mm/m64`	explicit	read
`PADDUSW xmm, xmm/m128`
`xmm`	explicit	read, write
`xmm/m128`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

PADDUSW mm, m64: mmx-mem
PADDUSW mm, mm: none in XED
PADDUSW xmm, xmm/m128: SSE_TYPE_4

Attributes

What else XED records about the forms. How to read.

PADDUSW mm, mm/m64: may abort a TSX transaction
PADDUSW xmm, m128: aligned memory operand

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to PADDUSW, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic Compiles to

Intrinsic	Compiles to
`_mm_adds_epu16` `__m128i _mm_adds_epu16(__m128i __a, __m128i __b)`	`PADDUSW xmm, xmm` Legacy -msse2 Clang's comment names VPADDUSB, the byte addition; this intrinsic adds unsigned words with saturation, and Clang emits PADDUSW or VPADDUSW.
`_mm_adds_pu16` `__m64 _mm_adds_pu16(__m64 __m1, __m64 __m2)`	`PADDUSW xmm, xmm` Legacy -msse2

_mm_adds_epu16 __m128i _mm_adds_epu16(__m128i __a, __m128i __b)

PADDUSW xmm, xmm Legacy -msse2

Clang's comment names VPADDUSB, the byte addition; this intrinsic adds unsigned words with saturation, and Clang emits PADDUSW or VPADDUSW.

_mm_adds_pu16 __m64 _mm_adds_pu16(__m64 __m1, __m64 __m2)

PADDUSW xmm, xmm Legacy -msse2

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`PENTIUMMMX` MMX	MMX `CPUID.01H:EDX[23]` MMX	Every x86-64 processor in XED’s model and Zen 3 to Zen 6
`SSE2` SSE2	SSE2 `CPUID.01H:EDX[26]` SSE2	Every x86-64 processor in XED’s model and Zen 3 to Zen 6

More MMX instructions

All 47 MMX instructions

More SSE2 instructions

All 124 SSE2 instructions

In compiled code#