PADDW instruction (MMX, SSE2)

PADDW adds words element by element and keeps the low 16 bits of each sum, wrapping around the same way for signed and unsigned words: 8 in an XMM register, 4 in an MMX register. PADDB covers what the family’s legacy forms share. On Zen 5, the recorded paddw xmm4, [mem] turned 7FFFh plus 0001h into 8000h (32767 plus 1 wrapping to -32768) and FFFFh plus FFFFh into FFFEh, leaving bits 255:128 of the register as they were (see mixing SSE and AVX). The additions that clamp instead of wrapping are PADDSW for signed words and PADDUSW for unsigned ones.

Words in compiled code

In our builds at -O2 for the x86-64 baseline:

int16_t and uint16_t arrays. a[i] = b[i] + c[i] is one PADDW per 8 words in GCC 14 and Clang 23, both operands loaded by MOVDQU.
Widening sums of bytes. (int16_t)b[i] + (int16_t)c[i] over int8_t arrays, which keeps the full range of the sum in a word, has both compilers sign-extend each byte to a word before PADDW, but differently: GCC compares each input with a zeroed register by PCMPGTB to get a sign mask and interleaves it with PUNPCKLBW and PUNPCKHBW, where Clang duplicates each byte onto itself with PUNPCKLBW and shifts right by 8 with PSRAW instead.

AMD’s latency spreadsheet for Zen 5 gives PADDW one cycle, four per cycle, on all four vector pipes. The MMX form came with MMX and the XMM form with SSE2, whose memory operand must be aligned to 16 bytes. VPADDW is the VEX and EVEX form; PADDQ takes quadword elements.

Forms

Every encoding of PADDW that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`PADDW mm, m64` PADDW_MMXq_MEMq	`NP 0F FD /r`	MMX
`PADDW mm, mm` PADDW_MMXq_MMXq	`NP 0F FD /r`	MMX
`PADDW xmm, m128` PADDW_XMMdq_MEMdq	`66 0F FD /r`	SSE2
`PADDW xmm, xmm` PADDW_XMMdq_XMMdq	`66 0F FD /r`	SSE2

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Element-wise: each word of the result comes from the word in the same place in each source.

Every word works alike: 4 and 8 words in the mm and xmm forms.

Result word i comes from word i of xmm1 and xmm2. Result words 7 to 0: a7+b7, a6+b6, a5+b5, a4+b4, a3+b3, a2+b2, a1+b1, a0+b0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

PADDW mm, mm/m64

for i in range(4):
    mm1.w[i] = mm1.w[i] + src2.w[i]
# x87: TOP = 0, all tags valid, bits 79:64 of mm1's register all ones

Run on AMD Zen 5 (EPYC 9645): 2 cases.

PADDW xmm, xmm/m128

for i in range(8):
    xmm1.w[i] = xmm1.w[i] + src2.w[i]
# bits 128 and up of the register are unchanged

Run on AMD Zen 5 (EPYC 9645): 2 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`PADDW mm, mm/m64`
`mm`	explicit	read, write
`mm/m64`	explicit	read
`PADDW xmm, xmm/m128`
`xmm`	explicit	read, write
`xmm/m128`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

PADDW mm, mm/m64: mmx-mem
PADDW xmm, xmm/m128: SSE_TYPE_4

Attributes

What else XED records about the forms. How to read.

PADDW mm, mm/m64: may abort a TSX transaction
PADDW xmm, m128: aligned memory operand

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to PADDW, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`_mm_add_epi16` `__m128i _mm_add_epi16(__m128i __a, __m128i __b)`	`PADDW xmm, xmm` Legacy -msse2
`_mm_add_pi16` `__m64 _mm_add_pi16(__m64 __m1, __m64 __m2)`	`PADDW xmm, xmm` Legacy -msse2

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`PENTIUMMMX` MMX	MMX `CPUID.01H:EDX[23]` MMX	Every x86-64 processor in XED’s model and Zen 3 to Zen 6
`SSE2` SSE2	SSE2 `CPUID.01H:EDX[26]` SSE2	Every x86-64 processor in XED’s model and Zen 3 to Zen 6

More MMX instructions

All 47 MMX instructions

More SSE2 instructions

All 124 SSE2 instructions

Words in compiled code#