PAND instruction (MMX, SSE2)

PAND is the bitwise AND of two 64-bit MMX or 128-bit XMM operands, with the result written over the first. VPAND, the VEX form, covers what the operation is for in vector code; PANDN, POR and PXOR are the rest of the family. What the legacy forms add:

The XMM form came with SSE2, so every x86-64 processor has it. It leaves bits 128 and up of the register as they were (see mixing SSE and AVX), and its memory operand must be aligned to 16 bytes.
The MMX form works on the MMX registers, which live in the x87 registers: as the Operation section shows, it also sets the x87 top of stack to 0, marks every register valid and fills bits 79:64 of its own with ones, so x87 code afterwards needs EMMS first. Its 8-byte memory operand may be at any address: Intel’s table for these instructions lists no alignment fault, only #AC when alignment checking is on (Volume 3, Table 25-7). On Zen 5, the recorded pand mm1, qword ptr [mem] turned 0Fh AND 01h into 01h.

In baseline code

In our builds at -O2, for the x86-64 baseline and for -march=x86-64-v2, over fixed-size arrays:

GCC 14 uses PAND for every integer AND, a[i] = b[i] & c[i] over uint32_t and _mm_and_si128 included. Clang 23 uses ANDPS, a byte shorter for lacking the 66 prefix, for that loop, whose result is only stored, and PAND where integer arithmetic follows, as in (b[i] & c[i]) + 1.
b[i] > c[i] ? b[i] : 0 over int is PCMPGTD and PAND in both. Keeping the larger of the two takes PCMPGTD, PAND, PANDN and POR at the baseline, and one PMAXSD with x86-64-v2.
Narrowing uint16_t to uint8_t is a PAND with 00FFh in every word before PACKUSWB, in both at the baseline.
Neither compiler emits the MMX form: _mm_and_si64 on __m64 values becomes PAND on XMM registers in GCC and ANDPS in Clang.

AMD’s latency spreadsheet for Zen 5 gives the XMM form one cycle and four per cycle.

Forms

Every encoding of PAND that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`PAND mm, m64` PAND_MMXq_MEMq	`NP 0F DB /r`	MMX
`PAND mm, mm` PAND_MMXq_MMXq	`NP 0F DB /r`	MMX
`PAND xmm, m128` PAND_XMMdq_MEMdq	`66 0F DB /r`	SSE2
`PAND xmm, xmm` PAND_XMMdq_XMMdq	`66 0F DB /r`	SSE2

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Element-wise: each quadword of the result comes from the quadword in the same place in each source.

Every quadword works alike: 1 and 2 quadwords in the mm and xmm forms.

Result quadword i comes from quadword i of xmm1 and xmm2. Result quadwords 1 to 0: a1&b1, a0&b0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

PAND mm, mm/m64

i = 0
mm1.q[i] = mm1.q[i] & src2.q[i]
# x87: TOP = 0, all tags valid, bits 79:64 of mm1's register all ones

Run on AMD Zen 5 (EPYC 9645): 2 cases.

PAND xmm, xmm/m128

for i in range(2):
    xmm1.q[i] = xmm1.q[i] & src2.q[i]
# bits 128 and up of the register are unchanged

Run on AMD Zen 5 (EPYC 9645): 2 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`PAND mm, mm/m64`
`mm`	explicit	read, write
`mm/m64`	explicit	read
`PAND xmm, xmm/m128`
`xmm`	explicit	read, write
`xmm/m128`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

PAND mm, m64: mmx-mem
PAND mm, mm: none in XED
PAND xmm, xmm/m128: SSE_TYPE_4

Attributes

What else XED records about the forms. How to read.

PAND mm, mm/m64: may abort a TSX transaction
PAND xmm, m128: aligned memory operand

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to PAND, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`_mm_and_pd` `__m128d _mm_and_pd(__m128d __a, __m128d __b)`	`PAND xmm, xmm` Legacy -msse2
`_mm_and_si128` `__m128i _mm_and_si128(__m128i __a, __m128i __b)`	`PAND xmm, xmm` Legacy -msse2
`_mm_and_si64` `__m64 _mm_and_si64(__m64 __m1, __m64 __m2)`	`PAND xmm, xmm` Legacy -msse2

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`PENTIUMMMX` MMX	MMX `CPUID.01H:EDX[23]` MMX	Every x86-64 processor in XED’s model and Zen 3 to Zen 6
`SSE2` SSE2	SSE2 `CPUID.01H:EDX[26]` SSE2	Every x86-64 processor in XED’s model and Zen 3 to Zen 6

More MMX instructions

All 47 MMX instructions

More SSE2 instructions

All 124 SSE2 instructions

In baseline code#