PANDN instruction (MMX, SSE2)

PANDN inverts its first operand and ANDs the result with the second, writing over the first: pandn xmm0, xmm1 leaves NOT xmm0 AND xmm1 in XMM0, so the value that gets inverted is also the one that is lost. VPANDN covers the operand order and the VEX form, and PAND what the legacy encodings share: the SSE2 XMM form, which leaves bits 128 and up of the register as they were (see mixing SSE and AVX) and needs a memory operand aligned to 16 bytes, and the MMX form with its x87 side effects.

Zen 5’s recorded cases show the inversion at work:

pandn xmm1, xmm2 with all ones in XMM2 gave NOT xmm1, turning 7FFFFFFFFFFFFFFFh into 8000000000000000h and back: with all ones as the second operand, PANDN is the NOT that SSE lacks.
pandn mm3, mm3 gave zero from 1, as NOT x AND x does for any x. AMD’s Zen 5 guide lists only the VEX and EVEX VPANDN of a register with itself among the zeroing idioms (Section 2.9.2), and Intel’s list of dependency-breaking idioms does not name PANDN at all (Section 3.5.1.7).

Selecting without a blend

Before SSE4.1, a choice between two vectors under a compare mask is PAND, PANDN and POR, the sequence Intel’s optimization manual shows with MMX registers and PCMPGTW (Section 5.6, Example 5-26); PANDN consumes the mask, which needs no copy. In our builds at -O2 for the x86-64 baseline, GCC 14 and Clang 23 compile b[i] > c[i] ? b[i] : c[i] over int arrays to exactly that, after a PCMPGTD, and b[i] > c[i] ? 0 : b[i] to PCMPGTD and a lone PANDN. With -march=x86-64-v2 the first becomes PMAXSD.

For b[i] & ~c[i] the two differ: GCC makes all ones with PCMPEQD, inverts c with PXOR and ANDs with PAND, three instructions where one would do, while Clang uses ANDNPS, the same operation in the floating-point domain. GCC compiles _mm_andnot_si128(a, b) to PANDN, which inverts a.

In the optimization guide

What the optimization guide says about PANDN, a line per claim. Each links to the claim in the guide, with its sources and where they differ.

Skylake to Cooper Lake

Integer execution: xor, sub and the vector pxor, xorps, pandn, psub and pcmpgt of a register with itself zero it without an execution unit, four a cycle, for 32-bit and 64-bit and all vector registers.

Forms

Every encoding of PANDN that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`PANDN mm, m64` PANDN_MMXq_MEMq	`NP 0F DF /r`	MMX
`PANDN mm, mm` PANDN_MMXq_MMXq	`NP 0F DF /r`	MMX
`PANDN xmm, m128` PANDN_XMMdq_MEMdq	`66 0F DF /r`	SSE2
`PANDN xmm, xmm` PANDN_XMMdq_XMMdq	`66 0F DF /r`	SSE2

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Element-wise: each quadword of the result comes from the quadword in the same place in each source.

Every quadword works alike: 1 and 2 quadwords in the mm and xmm forms.

Result quadword i comes from quadword i of xmm1 and xmm2. Result quadwords 1 to 0: ~a1&b1, ~a0&b0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

PANDN mm, mm/m64

i = 0
mm1.q[i] = ~mm1.q[i] & src2.q[i]
# x87: TOP = 0, all tags valid, bits 79:64 of mm1's register all ones

Run on AMD Zen 5 (EPYC 9645): 2 cases.

PANDN xmm, xmm/m128

for i in range(2):
    xmm1.q[i] = ~xmm1.q[i] & src2.q[i]
# bits 128 and up of the register are unchanged

Run on AMD Zen 5 (EPYC 9645): 2 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`PANDN mm, mm/m64`
`mm`	explicit	read, write
`mm/m64`	explicit	read
`PANDN xmm, xmm/m128`
`xmm`	explicit	read, write
`xmm/m128`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

PANDN mm, m64: mmx-mem
PANDN mm, mm: none in XED
PANDN xmm, xmm/m128: SSE_TYPE_4

Attributes

What else XED records about the forms. How to read.

PANDN mm, mm/m64: may abort a TSX transaction
PANDN xmm, m128: aligned memory operand

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to PANDN, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`_mm_andnot_pd` `__m128d _mm_andnot_pd(__m128d __a, __m128d __b)`	`PANDN xmm, xmm` Legacy -msse2
`_mm_andnot_si128` `__m128i _mm_andnot_si128(__m128i __a, __m128i __b)`	`PANDN xmm, xmm` Legacy -msse2
`_mm_andnot_si64` `__m64 _mm_andnot_si64(__m64 __m1, __m64 __m2)`	`PANDN xmm, xmm` Legacy -msse2

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`PENTIUMMMX` MMX	MMX `CPUID.01H:EDX[23]` MMX	Every x86-64 processor in XED’s model and Zen 3 to Zen 6
`SSE2` SSE2	SSE2 `CPUID.01H:EDX[26]` SSE2	Every x86-64 processor in XED’s model and Zen 3 to Zen 6

More MMX instructions

All 47 MMX instructions

More SSE2 instructions

All 124 SSE2 instructions

Selecting without a blend#