PAUSE

PAUSE belongs in the body of a spin-wait loop: the loop that rereads a lock word or a flag until another thread changes it. The usual shape is to try the atomic operation (a LOCK CMPXCHG or XCHG), and while it fails, spin on plain loads with a PAUSE in each iteration until the lock looks free, then try again. The PAUSE gives the core’s resources to the other hardware thread, saves power and makes the loop leave faster when the value changes.

Its encoding, F3 90, is NOP with a REP prefix, so it needs no CPUID check: processors that predate it run it as a NOP. GCC 14 even prints it as rep nop, where Clang 23 prints pause.

How long one PAUSE waits differs widely, by the vendors’ optimization manuals:

• about 10 cycles on Intel’s cores before Skylake, and up to 140 on the Skylake client cores;
• about 64 cycles, during which the thread dispatches nothing, on Zen 5.

A loop that waits a fixed number of PAUSEs can therefore wait more than ten times longer on one processor than on another. Intel’s optimization manual suggests bounding the wait by time read with RDTSC instead, and, for a contended lock, doubling the number of PAUSEs after each failed attempt up to a limit. For waits of thousands of cycles or more, it advises giving the processor back to the operating system, through a futex on Linux, rather than spinning.

Under virtualization a spinning guest may wait for a virtual processor that is not running at all. Intel’s VMX can exit to the hypervisor when a guest keeps executing PAUSE in a loop (PAUSE-loop exiting), and AMD’s SVM after a set number of PAUSEs (pause filtering); the hypervisor can then run another virtual processor instead.

To wait without spinning, see UMWAIT and TPAUSE on Intel’s processors and MWAITX on AMD’s.

In the optimization guide

What the optimization guide says about PAUSE, a line per claim. Each links to the claim in the guide, with its sources and where they differ.

Branches

• The cost of a misprediction: A tight spin-wait loop ends in a flush of its own: its loads run ahead of the store that releases it, and the processor must discard them to keep memory order.

Memory

• Sharing between cores: A contended lock is best taken by spinning on a plain load with PAUSE and trying cmpxchg only when it looks free, with backoff.

Crestmont and Gracemont

• Hybrid processors: Intel advises against pinning threads to cores and for waiting with UMWAIT, TPAUSE or PAUSE. sources differ

Golden Cove and Raptor Cove

• Threads and hybrid parts: On Alder Lake and Raptor Lake, Thread Director tells the operating system how each thread would fare on either kind of core. sources differ

Silvermont to Goldmont Plus

• Out-of-order and in-order execution: From Goldmont on, pause waits about as long as on Skylake, to save power in spin loops; see Skylake for what that means for code that spins.

Skylake to Cooper Lake

• Threads: PAUSE takes up to about 140 cycles, against about 10 on earlier cores, to leave the core to the sibling thread and save power. sources differ

Zen 3

• Two threads on a core: PAUSE stops the thread’s dispatch for about 64 cycles, which saves power and leaves resources to the other thread while a spin loop waits.

Zen 4

• Two threads on a core: PAUSE stops the thread’s dispatch for about 64 cycles, which saves power and leaves resources to the other thread while a spin loop waits.

Zen 5

• Two threads on a core: PAUSE stops the thread’s dispatch for about 64 cycles, which saves power and leaves resources to the other thread while a spin loop waits.

Forms

Latency and throughput

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

pass                             # a hint that the code spins, waiting
                                 # for a value that another processor
                                 # writes: the processor waits a short
                                 # while, which differs between models,
                                 # and leaves the loop sooner when the
                                 # value changes; nothing else happens
# F3 90 is NOP with a REP prefix, which older processors run as NOP

Operands

None: XED lists no operands for this form.

Flags

None: XED records no flag that the forms test or change.

Attributes

What else XED records about the forms. How to read.

All forms

may abort a TSX transaction

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More General-purpose instructions

• LES
• LFS
• LGS
• LODS
• LOOP
• LOOPE
• LOOPNE
• LSS
• MOV
• MOVS
• MOVSX
• MOVSXD
• MOVZX
• MUL
• NEG
• NOP
• NOT
• OR
• OUT
• OUTS
• POP
• POPA
• POPF
• PUSH
• PUSHA
• PUSHF
• RCL
• RCR
• RET
• ROL
• ROR
• SALC
• SAR
• SBB
• SCAS
• SETcc
• SHL
• SHLD
• SHR
• SHRD

All 109 General-purpose instructions