PAVGB instruction (SSE, SSE2)

PAVGB averages unsigned bytes and rounds halves up: each result byte is (a + b + 1) >> 1, worked out with a ninth bit so that the sum cannot overflow (Intel’s optimization manual explains the carry, Section 6.6.11). FFh and FFh average to FFh, 0 and 1 to 1.

The rounding is half up, and that is what decides whether a compiler can use it. GCC 14 and Clang 23 at -O2 compile r[i] = (p[i] + q[i] + 1) >> 1 over uint8_t arrays to PAVGB alone, 16 bytes per instruction. The truncating average (p[i] + q[i]) >> 1 is a different result for every odd sum, so neither compiler uses PAVGB for it; both build it from shifts, ANDs and additions instead, such as (p & q) + ((p ^ q) >> 1) byte by byte.

Variations

Rounding down. PAVGB of a and b, minus (a ^ b) & 1, gives the truncating average with three more instructions (PXOR, PAND with a vector of ones and PSUBB), since the two results differ by one exactly when the sum is odd.
Signed bytes. There is no signed average, but flipping the top bit of both inputs with PXOR and 80h, which maps -128..127 onto 0..255 in order, then flipping the result back gives a signed average rounded up.
Repeated averaging. Averaging four values as the average of two averages rounds up twice and can come out one too high: 0, 0, 0 and 1 give 1, where the rounded mean is 0.

It suits pixel data, where halving an image or interpolating between two rows takes bytes in and must give bytes out. PAVGW does the same for unsigned words; there are no doubleword or quadword forms.

The MMX form came with SSE, the XMM form with SSE2, and the legacy XMM form needs a memory operand aligned to 16 bytes. VPAVGB is the VEX and EVEX form.

In the optimization guide

What the optimization guide says about PAVGB, a line per claim. Each links to the claim in the guide, with its sources and where they differ.

Skylake to Cooper Lake

Vectors on all parts: Many MMX instructions, among them the saturating additions and subtractions, comparisons, pmaxsw, pminsw, pavgb and pabsb, run on one port at half Broadwell’s rate.

Forms

Every encoding of PAVGB that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`PAVGB mm, m64` PAVGB_MMXq_MEMq	`NP 0F E0 /r`	SSE
`PAVGB mm, mm` PAVGB_MMXq_MMXq	`NP 0F E0 /r`	SSE
`PAVGB xmm, m128` PAVGB_XMMdq_MEMdq	`66 0F E0 /r`	SSE2
`PAVGB xmm, xmm` PAVGB_XMMdq_XMMdq	`66 0F E0 /r`	SSE2

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Element-wise: each byte of the result comes from the byte in the same place in each source.

Shown: bytes 7 to 0. Every byte works alike: 8 and 16 bytes in the mm and xmm forms.

Result byte i comes from byte i of xmm1 and xmm2. Result bytes 7 to 0: r7, r6, r5, r4, r3, r2, r1, r0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

PAVGB mm, mm/m64

for i in range(8):
    a = mm1.b[i]
    b = src2.b[i]
    mm1.b[i] = (a + b + 1) >> 1
# x87: TOP = 0, all tags valid, bits 79:64 of mm1's register all ones

Run on AMD Zen 5 (EPYC 9645): 2 cases.

PAVGB xmm, xmm/m128

for i in range(16):
    a = xmm1.b[i]
    b = src2.b[i]
    xmm1.b[i] = (a + b + 1) >> 1
# bits 128 and up of the register are unchanged

Run on AMD Zen 5 (EPYC 9645): 2 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`PAVGB mm, mm/m64`
`mm`	explicit	read, write
`mm/m64`	explicit	read
`PAVGB xmm, xmm/m128`
`xmm`	explicit	read, write
`xmm/m128`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

PAVGB mm, m64: mmx-mem
PAVGB mm, mm: none in XED
PAVGB xmm, xmm/m128: SSE_TYPE_4

Attributes

What else XED records about the forms. How to read.

PAVGB mm, mm/m64: may abort a TSX transaction
PAVGB xmm, m128: aligned memory operand

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to PAVGB, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`_mm_avg_epu8` `__m128i _mm_avg_epu8(__m128i __a, __m128i __b)`	`PAVGB xmm, xmm` Legacy -msse2
`_mm_avg_pu8` `__m64 _mm_avg_pu8(__m64 __a, __m64 __b)`	`PAVGB xmm, xmm` Legacy -msse2

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`SSE` SSE	SSE `CPUID.01H:EDX[25]` SSE	Every x86-64 processor in XED’s model and Zen 3 to Zen 6
`SSE2` SSE2	SSE2 `CPUID.01H:EDX[26]` SSE2	Every x86-64 processor in XED’s model and Zen 3 to Zen 6

More SSE instructions

All 65 SSE instructions

More SSE2 instructions

All 124 SSE2 instructions

Variations#