PAVGUSB instruction (3DNow!)

Forms

Every encoding of PAVGUSB that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`PAVGUSB mm, m64` PAVGUSB_MMXq_MEMq	`0F 0F /r BF`	3DNow
`PAVGUSB mm, mm` PAVGUSB_MMXq_MMXq	`0F 0F /r BF`	3DNow

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Element-wise: each byte of the result comes from the byte in the same place in each source.

Result byte i comes from byte i of mm1 and mm2. Result bytes 7 to 0: r7, r6, r5, r4, r3, r2, r1, r0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

features = cpuid_leaf(0x80000001, 0)[3]
if not features >> 31 & 1:
    fault(UD)  # CPUID: no 3DNow!
for i in range(8):
    a = mm1.b[i]
    b = src2.b[i]
    mm1.b[i] = (a + b + 1) >> 1
# x87: TOP = 0, all tags valid, bits 79:64 of mm1's register all ones

Run on AMD Zen 5 (EPYC 9645): 2 cases. Its cases ran where CPUID reported no 3DNow!, and every one raised an exception.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`PAVGUSB mm, mm/m64`
`mm`	explicit	read, write
`mm/m64`	explicit	read

Flags

None: XED records no flag that the forms test or change.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`3DNOW` 3DNow!	3DNow `CPUID.80000001H:EDX[31]` 3DNow	K10 (Family 10h)

PAVGUSB