PAVGW instruction (SSE, SSE2)

PAVGW averages unsigned words and rounds halves up: each result is (a + b + 1) >> 1, computed with a seventeenth bit so that the sum cannot overflow. PAVGB is the same for bytes, and its page describes the rounding and the variations built on it. On Zen 5, the recorded cases show the wide sum at work: FFFFh and 0001h averaged to 8000h, FFFFh and 8000h to C000h, and 7FFFh and 0001h to 4000h. A signed reading would have given 0 for the first pair; the instruction has no signed form.

In compiled code

GCC 14 and Clang 23 at -O2 compile a[i] = (b[i] + c[i] + 1) >> 1 over uint16_t to PAVGW alone, 8 words per instruction, and _mm_avg_epu16 to the same. The C needs no care about overflow, since the words are added as int. Other averages are built from shifts and logic:

Rounding down. (b[i] + c[i]) >> 1 gives a different result for every odd sum, so neither compiler uses PAVGW. Clang computes (b & c) + ((b ^ c) >> 1); GCC adds the two halves b >> 1 and c >> 1 and the carry b & c & 1.
Signed words. For int16_t, Clang uses (b | c) - ((b ^ c) >> 1) with the arithmetic PSRAW, five instructions per vector. GCC widens to doublewords, adds, shifts with PSRAD and narrows again, which takes more than twenty instructions for the SSE2 baseline and still about fifteen with -march=x86-64-v2.

Intel’s optimization manual describes the two averages together (Section 6.6.11) and counts the MMX form of PAVGW among those that Skylake runs at half the throughput of earlier cores (Section 15.16.5). AMD’s latency spreadsheet for Zen 5 gives the XMM form two cycles, four per cycle, one more cycle than PADDW. The MMX form came with SSE, the XMM form with SSE2; the legacy XMM form keeps bits 255:128 of its register (see mixing SSE and AVX) and needs a memory operand aligned to 16 bytes. VPAVGW is the VEX and EVEX form.

Forms

Every encoding of PAVGW that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`PAVGW mm, m64` PAVGW_MMXq_MEMq	`NP 0F E3 /r`	SSE
`PAVGW mm, mm` PAVGW_MMXq_MMXq	`NP 0F E3 /r`	SSE
`PAVGW xmm, m128` PAVGW_XMMdq_MEMdq	`66 0F E3 /r`	SSE2
`PAVGW xmm, xmm` PAVGW_XMMdq_XMMdq	`66 0F E3 /r`	SSE2

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Element-wise: each word of the result comes from the word in the same place in each source.

Every word works alike: 4 and 8 words in the mm and xmm forms.

Result word i comes from word i of xmm1 and xmm2. Result words 7 to 0: r7, r6, r5, r4, r3, r2, r1, r0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

PAVGW mm, mm/m64

for i in range(4):
    a = mm1.w[i]
    b = src2.w[i]
    mm1.w[i] = (a + b + 1) >> 1
# x87: TOP = 0, all tags valid, bits 79:64 of mm1's register all ones

Run on AMD Zen 5 (EPYC 9645): 2 cases.

PAVGW xmm, xmm/m128

for i in range(8):
    a = xmm1.w[i]
    b = src2.w[i]
    xmm1.w[i] = (a + b + 1) >> 1
# bits 128 and up of the register are unchanged

Run on AMD Zen 5 (EPYC 9645): 2 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`PAVGW mm, mm/m64`
`mm`	explicit	read, write
`mm/m64`	explicit	read
`PAVGW xmm, xmm/m128`
`xmm`	explicit	read, write
`xmm/m128`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

PAVGW mm, m64: mmx-mem
PAVGW mm, mm: none in XED
PAVGW xmm, xmm/m128: SSE_TYPE_4

Attributes

What else XED records about the forms. How to read.

PAVGW mm, mm/m64: may abort a TSX transaction
PAVGW xmm, m128: aligned memory operand

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to PAVGW, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`_mm_avg_epu16` `__m128i _mm_avg_epu16(__m128i __a, __m128i __b)`	`PAVGW xmm, xmm` Legacy -msse2
`_mm_avg_pu16` `__m64 _mm_avg_pu16(__m64 __a, __m64 __b)`	`PAVGW xmm, xmm` Legacy -msse2

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`SSE` SSE	SSE `CPUID.01H:EDX[25]` SSE	Every x86-64 processor in XED’s model and Zen 3 to Zen 6
`SSE2` SSE2	SSE2 `CPUID.01H:EDX[26]` SSE2	Every x86-64 processor in XED’s model and Zen 3 to Zen 6

More SSE instructions

All 65 SSE instructions

More SSE2 instructions

All 124 SSE2 instructions

In compiled code#