PBLENDW instruction (SSE4.1)

PBLENDW picks each of the eight words of its result from one of two sources by a constant: bit i of the immediate set takes word i from the source operand, clear keeps the destination’s. It came with SSE4.1, beside BLENDPS and BLENDPD for floats; VBLENDPS shows how blends stand in for shuffles that leave every element in place. On Zen 5, pblendw xmm8, xmm15, 0x47 took words 0, 1, 2 and 6 from XMM15 and kept the rest, and bits 128 and up of ZMM8 kept their values, as with every legacy SSE instruction. A memory operand must be aligned to 16 bytes.

SSE4.1’s only integer blend

SSE4.1 has no doubleword or quadword blend by immediate for integers, so a word blend with its bits in pairs or fours stands in. At -O2 with -march=x86-64-v2, GCC 14 compiles __builtin_shufflevector(a, b, 0, 5, 2, 7) on four ints to PBLENDW with immediate 33h, and the quadword version to 0Fh, in both cases with MOVDQA copies around it, since the legacy form overwrites its first operand. Clang 23 uses BLENDPS for both. With -march=x86-64-v3, GCC moves to VPBLENDD for doublewords but keeps VPBLENDW for quadwords, and Clang keeps VBLENDPS.

For real words there is no alternative: both compilers emit pblendw xmm0, xmm1, 1 to replace word 0 of a vector with word 0 of another, and one PBLENDW for alternating words (GCC with the sources swapped and immediate 55h, Clang with AAh).

When the choice is made at run time

The immediate fixes the pattern when the code is compiled. A choice per element at run time takes PBLENDVB instead, which also serves words: a word compare sets both bytes of a word alike, so a[i] > b[i] ? a[i] : 7 over int16_t compiles to PCMPGTW and PBLENDVB in both compilers at x86-64-v2, and to the AND, ANDN and OR of three logic instructions for the SSE2 baseline.

VPBLENDW, the VEX form, applies the same eight bits to each 128-bit lane of a YMM register. There is no EVEX form: AVX512BW blends words under a mask register with VPBLENDMW.

Forms

Every encoding of PBLENDW that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`PBLENDW xmm, m128, imm8` PBLENDW_XMMdq_MEMdq_IMMb	`66 0F 3A 0E /r ib`	SSE4.1
`PBLENDW xmm, xmm, imm8` PBLENDW_XMMdq_XMMdq_IMMb	`66 0F 3A 0E /r ib`	SSE4.1

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Blend by immediate: each word comes from xmm2 where its bit of imm8 is 1, else from xmm1.

Example: imm8 = 0xB2 (1011 0010 in binary).

Result words 7 to 0: b7, a6, b5, b4, a3, a2, b1, a0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(8):
    if imm8 >> i % 8 & 1:
        xmm1.w[i] = src2.w[i]
    else:
        xmm1.w[i] = xmm1.w[i]
# bits 128 and up of the register are unchanged

Run on AMD Zen 5 (EPYC 9645): 2 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`PBLENDW xmm, xmm/m128, imm8`
`xmm`	explicit	read, write
`xmm/m128`	explicit	read
`imm8`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms: SSE_TYPE_4

Attributes

What else XED records about the forms. How to read.

Memory forms: aligned memory operand

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to PBLENDW, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`_mm_blend_epi16` `__m128i _mm_blend_epi16(__m128i V1, __m128i V2, const int M)`	`PBLENDW xmm, xmm, imm8` Legacy -msse4.1

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`SSE4` SSE4.1	SSE4.1 `CPUID.01H:ECX[19]` SSE4.1	Penryn, Nehalem, Westmere, Sandy Bridge, Ivy Bridge, Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Silvermont, Goldmont, Goldmont Plus, Tremont, Snow Ridge, Lakefield, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, K10 (Family 10h), Bulldozer, Piledriver, Zen, Zen+, Zen 2, Zen 3, Zen 4, Zen 5, Zen 6 Note: XED's AMD_K10 inherits everything from its Westmere chip, including SSSE3, SSE4.1, SSE4.2, AES-NI and PCLMULQDQ; GCC's -march=amdfam10 has none of them.

More SSE4.1 instructions

All 49 SSE4.1 instructions

SSE4.1’s only integer blend#

When the choice is made at run time#