PBNDKB

PBNDKB wraps a pair of storage encryption keys so that only the platform that wrapped them can use them, later, through PCONFIG, which programs the engine of Intel’s Total Storage Encryption (TSE). RBX holds the address of a 256-byte input bind structure and RCX that of the output; the two must differ, be canonical and be 256-byte aligned. The input carries the two 256-bit keys, a data key and a tweak key, at bytes 64 to 127, a 32-byte challenge of the software’s choosing at bytes 128 to 159 and a control byte, 0 or 1, at byte 160. Bytes 16 to 23, 36 to 63 and 161 to 255 must be 0, and the MAC and IV fields, at bytes 0 and 24, are not used. Breaking any of these rules raises #GP(0).

What it computes#

The wrapping key is an HMAC-SHA-256 of the challenge under a 256-bit key that belongs to the platform. With it and a fresh random 96-bit IV, PBNDKB encrypts the 64 bytes of keys with AES-GCM, whose tag also covers 176 bytes of additional data: eight zero bytes, the IV, 28 zero bytes and the input’s bytes 128 to 255. The output keeps the layout, with the 16-byte tag at byte 0, the IV at 24, the encrypted keys at 64, the control byte at 160 and zeros elsewhere, the challenge included. PCONFIG’s leaf TSE_KEY_PROGRAM_WRAPPED takes that structure with the challenge put back by software, so the structure is of no use without it. With the control byte at 1, PBNDKB first XORs both keys with random bits, so that not even the software that ran it knows the keys the engine will use.

Result and requirements#

Success clears ZF and RAX. If the random number generator runs short of entropy, for the keys or the IV, PBNDKB sets ZF, puts 1 (ENTROPY_ERROR) in RAX and writes nothing; the SDM allows other, platform-specific, reasons too. CF, PF, AF, OF and SF are cleared either way. At a CPL other than 0 it raises #UD, not #GP, as it does outside 64-bit mode, without CPUID.(EAX=07H,ECX=1):EBX[1], which also reports the MSR IA32_TSE_CAPABILITY, and in a VMX guest without the tertiary control “enable PBNDKB”. Intel lists Panther Lake for TSE and PBNDKB. GCC 14.2.0 and Clang 23.1.2 have no intrinsic for it, though both assemblers encode pbndkb as 0F 01 C7. The probe runs at CPL 3 and ran no case; the Zen 5 behind its recorded cases, whose CPUID.(EAX=07H,ECX=1):EBX is 0, lacks the instruction anyway.

Forms

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

if CPL > 0:                      # and outside 64-bit mode, or
    fault(UD)                    # without CPUID's PBNDKB bit
a = rbx                          # the input bind structure
b = rcx                          # and where the output goes
if not canonical(a) or not canonical(b):
    fault(GP, 0)
if a == b or (a | b) & 0xFF:     # the same, or not 256-byte
    fault(GP, 0)                 # aligned
keys = load(a + 64, 512)         # BTENCDATA: the two keys
data = load(a + 128, 1024)       # BTDATA
ctrl = data >> 256 & 0xFF        # its byte 32: add random bits?
if load(a + 16, 64) or load(a + 36, 224):
    fault(GP, 0)                 # reserved bytes not 0
if ctrl > 1 or data >> 264:      # nor BTDATA's bytes 33 to 127
    fault(GP, 0)
ok = 1
if ctrl == 1:                    # the keys with 512 random bits
    ok = random_ready()          # added, when the generator has
    if ok:                       # them
        keys ^= random(512)
chal = low(data, 256)            # the challenge, 32 bytes
k = hmac_sha256(platform_key, chal, 32)
if ok:
    ok = random_ready()          # a random IV of 12 bytes
if ok:
    iv = random(96)
    aad = iv << 64 | data << 384  # 0 x 8, IV, 0 x 28, BTDATA
    c = gcm_encrypt(k, iv, keys, 64)
    mac = gcm_tag(k, iv, aad, 176, c, 64)
    out = mac | iv << 192 | c << 512
    store(b, 2048, out | ctrl << 1280)
    rax = 0                      # the challenge is not written
    zf = 0                       # out: BTDATA keeps byte 32 only
else:
    rax = 1                      # ENTROPY_ERROR: no structure
    zf = 1                       # written
cf = pf = af = of = sf = 0
# the input's MAC and IV are not read, or not used. The SDM gives no
# other reason of failure than 1, but allows the platform ones

Operands

Flags

None: XED records no flag that the forms test or change.

Attributes

What else XED records about the forms. How to read.

All forms

privileged: CPL 0 only

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.