PCMPEQB instruction (MMX, SSE2)

PCMPEQB compares 16 pairs of bytes (8 in the MMX form) and writes FFh where the two bytes are equal and 00h where they differ. Equality does not care about signs, so the one instruction serves signed and unsigned data alike; the ordered comparison, PCMPGTB, treats bytes as signed, and an unsigned one came only with AVX-512’s VPCMPUB. The all-ones or all-zeros result is a mask ready for PAND, PANDN and PBLENDVB.

Two idioms are worth knowing:

Byte search. Compare 16 bytes of data with a register that holds the wanted byte in every position, gather the result into a 16-bit mask with PMOVMSKB, and find the first match with TZCNT or BSF on that mask; a zero mask means no match in the block. Comparing with a zeroed register finds the terminating zero of a string. GCC 14 and Clang 23 at -O2 compile _mm_cmpeq_epi8 followed by _mm_movemask_epi8 to exactly these instructions.
All ones. Comparing a register with itself sets every byte to FFh, whatever the register held. Intel’s optimization manual starts its constants this way (all ones, then shifts), and AMD’s Zen 5 guide lists PCMPEQB, PCMPEQW, PCMPEQD and PCMPEQQ of a register with itself as a ones idiom, which does not wait for the register’s old value. Both compilers use PCMPEQD for it.

The legacy form with a memory operand needs it aligned to 16 bytes, as most legacy SSE instructions do (see MOVDQU). In AVX-512 the EVEX form of VPCMPEQB writes a mask register instead of a vector, which makes the PMOVMSKB step unnecessary. The MMX form is best avoided: Intel’s manual notes that Skylake runs the MMX forms of the PCMPEQ instructions at half the throughput of earlier processors.

Forms

Every encoding of PCMPEQB that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`PCMPEQB mm, m64` PCMPEQB_MMXq_MEMq	`NP 0F 74 /r`	MMX
`PCMPEQB mm, mm` PCMPEQB_MMXq_MMXq	`NP 0F 74 /r`	MMX
`PCMPEQB xmm, m128` PCMPEQB_XMMdq_MEMdq	`66 0F 74 /r`	SSE2
`PCMPEQB xmm, xmm` PCMPEQB_XMMdq_XMMdq	`66 0F 74 /r`	SSE2

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Element-wise: each byte of the result comes from the byte in the same place in each source.

Shown: bytes 7 to 0. Every byte works alike: 8 and 16 bytes in the mm and xmm forms.

Result byte i comes from byte i of xmm1 and xmm2. Result bytes 7 to 0: r7, r6, r5, r4, r3, r2, r1, r0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

PCMPEQB mm, mm/m64

for i in range(8):
    a = mm1.b[i]
    b = src2.b[i]
    mm1.b[i] = -1 if a == b else 0
# x87: TOP = 0, all tags valid, bits 79:64 of mm1's register all ones

Run on AMD Zen 5 (EPYC 9645): 2 cases.

PCMPEQB xmm, xmm/m128

for i in range(16):
    a = xmm1.b[i]
    b = src2.b[i]
    xmm1.b[i] = -1 if a == b else 0
# bits 128 and up of the register are unchanged

Run on AMD Zen 5 (EPYC 9645): 2 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`PCMPEQB mm, mm/m64`
`mm`	explicit	read, write
`mm/m64`	explicit	read
`PCMPEQB xmm, xmm/m128`
`xmm`	explicit	read, write
`xmm/m128`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

PCMPEQB mm, mm/m64: mmx-mem
PCMPEQB xmm, xmm/m128: SSE_TYPE_4

Attributes

What else XED records about the forms. How to read.

PCMPEQB mm, mm/m64: may abort a TSX transaction
PCMPEQB xmm, m128: aligned memory operand

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to PCMPEQB, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`_mm_cmpeq_epi8` `__m128i _mm_cmpeq_epi8(__m128i __a, __m128i __b)`	`PCMPEQB xmm, xmm` Legacy -msse2
`_mm_cmpeq_pi8` `__m64 _mm_cmpeq_pi8(__m64 __m1, __m64 __m2)`	`PCMPEQB xmm, xmm` Legacy -msse2

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`PENTIUMMMX` MMX	MMX `CPUID.01H:EDX[23]` MMX	Every x86-64 processor in XED’s model and Zen 3 to Zen 6
`SSE2` SSE2	SSE2 `CPUID.01H:EDX[26]` SSE2	Every x86-64 processor in XED’s model and Zen 3 to Zen 6

More MMX instructions

All 47 MMX instructions

More SSE2 instructions

All 124 SSE2 instructions