PCMPEQD instruction (MMX, SSE2)

PCMPEQD compares 4 pairs of doublewords (2 in the MMX form) and writes FFFFFFFFh where the two are equal and 00000000h where they differ. Equality does not care about signs, so it serves int32_t, uint32_t and pointers alike; the ordered comparison, PCMPGTD, treats doublewords as signed, and an unsigned one came only with AVX-512’s VPCMPUD. PCMPEQB covers what the family shares: the byte-search idiom with PMOVMSKB, and that comparing a register with itself sets every bit. On Zen 5, the recorded pcmpeqd xmm1, xmm2 turned 80000000h against FFFFFFFFh (-2147483648 against -1) into 00000000h and 80000000h against 80000000h into FFFFFFFFh, leaving bits 255:128 of the register as they were (see mixing SSE and AVX).

Building constants

PCMPEQD is the usual way compiled code gets a vector of all ones: AMD’s Zen 5 guide lists the legacy PCMPEQB, PCMPEQW, PCMPEQD and PCMPEQQ of a register with itself among its Ones Idioms, which do not wait for the register’s old value (Section 2.9.2), the counterpart to the Zeroing Idioms that use PXOR and the wrapping PSUB forms the same way. In our builds at -O2, GCC 14 reaches for it whenever a doubleword mask or constant needs every bit set: the saturating clamp described on PADDUSW’s page, for one, builds the saturated value FFFFFFFFh with pcmpeqd xmm6, xmm6 and uses it directly as the “true” side of a PAND/PANDN/POR select.

Masks and selects. a[i] = b[i] == c[i] ? -1 : 0 over int32_t is one PCMPEQD per 4 doublewords in both compilers, and b[i] == c[i] ? 0 : b[i] adds a PANDN.
Finding a match. _mm_cmpeq_epi32 followed by _mm_movemask_ps on the result reinterpreted as floats compiles to PCMPEQD and MOVMSKPS in both compilers, a 4-bit mask instead of the 16-bit one PMOVMSKB gives for bytes.

The legacy form’s memory operand must be aligned to 16 bytes, as most legacy SSE instructions require. AMD’s latency spreadsheet for Zen 5 gives it one cycle, four per cycle, on all four vector pipes. Intel’s optimization manual counts the MMX form among those that Skylake runs at half the throughput of earlier cores (Section 15.16.5); the MMX form came with the original MMX instruction set. VPCMPEQD is the VEX form for 128 and 256 bits, still writing a vector; its EVEX form writes a mask register instead, which makes the PMOVMSKB step unnecessary.

In the optimization guide

What the optimization guide says about PCMPEQD, a line per claim. Each links to the claim in the guide, with its sources and where they differ.

Out of order

Zeroing and dependency-breaking idioms: pcmpeqd xmm0, xmm0 and the other equality comparisons of a register with itself set every bit without waiting for the old value.

Zen 3

Integer execution: Register-to-register moves of general registers of 32 and 64 bits, xchg of them and moves of whole XMM and YMM registers take no execution cycle, nor do the zeroing idioms such as xor eax, eax and vpxor, which also break the dependency on the old value; sbb eax, eax depends only on the carry flag, and pcmpeqd xmm0, xmm0 sets all ones without waiting. sources differ

Forms

Every encoding of PCMPEQD that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`PCMPEQD mm, m64` PCMPEQD_MMXq_MEMq	`NP 0F 76 /r`	MMX
`PCMPEQD mm, mm` PCMPEQD_MMXq_MMXq	`NP 0F 76 /r`	MMX
`PCMPEQD xmm, m128` PCMPEQD_XMMdq_MEMdq	`66 0F 76 /r`	SSE2
`PCMPEQD xmm, xmm` PCMPEQD_XMMdq_XMMdq	`66 0F 76 /r`	SSE2

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Element-wise: each doubleword of the result comes from the doubleword in the same place in each source.

Every doubleword works alike: 2 and 4 doublewords in the mm and xmm forms.

Result doubleword i comes from doubleword i of xmm1 and xmm2. Result doublewords 3 to 0: r3, r2, r1, r0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

PCMPEQD mm, mm/m64

for i in range(2):
    a = mm1.d[i]
    b = src2.d[i]
    mm1.d[i] = -1 if a == b else 0
# x87: TOP = 0, all tags valid, bits 79:64 of mm1's register all ones

Run on AMD Zen 5 (EPYC 9645): 2 cases.

PCMPEQD xmm, xmm/m128

for i in range(4):
    a = xmm1.d[i]
    b = src2.d[i]
    xmm1.d[i] = -1 if a == b else 0
# bits 128 and up of the register are unchanged

Run on AMD Zen 5 (EPYC 9645): 2 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`PCMPEQD mm, mm/m64`
`mm`	explicit	read, write
`mm/m64`	explicit	read
`PCMPEQD xmm, xmm/m128`
`xmm`	explicit	read, write
`xmm/m128`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

PCMPEQD mm, mm/m64: mmx-mem
PCMPEQD xmm, xmm/m128: SSE_TYPE_4

Attributes

What else XED records about the forms. How to read.

PCMPEQD mm, mm/m64: may abort a TSX transaction
PCMPEQD xmm, m128: aligned memory operand

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to PCMPEQD, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`_mm_cmpeq_epi32` `__m128i _mm_cmpeq_epi32(__m128i __a, __m128i __b)`	`PCMPEQD xmm, xmm` Legacy -msse2
`_mm_cmpeq_pi32` `__m64 _mm_cmpeq_pi32(__m64 __m1, __m64 __m2)`	`PCMPEQD xmm, xmm` Legacy -msse2

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`PENTIUMMMX` MMX	MMX `CPUID.01H:EDX[23]` MMX	Every x86-64 processor in XED’s model and Zen 3 to Zen 6
`SSE2` SSE2	SSE2 `CPUID.01H:EDX[26]` SSE2	Every x86-64 processor in XED’s model and Zen 3 to Zen 6

More MMX instructions

All 47 MMX instructions

More SSE2 instructions

All 124 SSE2 instructions

Building constants#