PCMPEQW instruction (MMX, SSE2)

PCMPEQW compares words, 8 pairs in an XMM register or 4 in an MMX register, and sets each word of the destination to FFFFh where the two are equal and to 0000h where they differ. Equality ignores the sign, so it serves int16_t, uint16_t and 16-bit characters alike. On Zen 5, the recorded pcmpeqw xmm7, xmm11 gave FFFFh for 7FFFh against 7FFFh and for 0008h against 0008h, and 0000h for 0000h against 8000h, and left bits 255:128 of the register as they were (see mixing SSE and AVX). PCMPEQB describes the family: the masks it makes, the byte search with PMOVMSKB, and the all-ones idiom of a register compared with itself, which AMD’s Zen 5 guide lists for PCMPEQW as well (Section 2.9.2).

Words in compiled code

In our builds at -O2 for the x86-64 baseline:

Masks and selects. a[i] = b[i] == c[i] ? -1 : 0 over int16_t is one PCMPEQW per 8 words in GCC 14 and Clang 23, and b[i] == c[i] ? 0 : b[i] adds a PANDN.
Searching 16-bit text. A search for the first matching word with _mm_cmpeq_epi16 and _mm_movemask_epi8 compiles to PCMPEQW and PMOVMSKB, which gives two mask bits per word; both compilers find the lowest set bit with rep bsf, the encoding of TZCNT, and shift it right by one for the index.
Unsigned order. For b[i] > c[i] over uint16_t, GCC subtracts with unsigned saturation, PSUBUSW, and compares the difference with zero by two PCMPEQWs, the second inverting the first, as the PCMPGTW page describes.

AMD’s latency spreadsheet for Zen 5 gives the XMM form one cycle, four per cycle. Intel’s optimization manual counts the MMX form among those that Skylake runs at half the throughput of earlier cores (Section 15.16.5). The MMX form came with MMX and the XMM form with SSE2, whose memory operand must be aligned to 16 bytes. VPCMPEQW is the VEX and EVEX form, the EVEX one writing a mask register.

Forms

Every encoding of PCMPEQW that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`PCMPEQW mm, m64` PCMPEQW_MMXq_MEMq	`NP 0F 75 /r`	MMX
`PCMPEQW mm, mm` PCMPEQW_MMXq_MMXq	`NP 0F 75 /r`	MMX
`PCMPEQW xmm, m128` PCMPEQW_XMMdq_MEMdq	`66 0F 75 /r`	SSE2
`PCMPEQW xmm, xmm` PCMPEQW_XMMdq_XMMdq	`66 0F 75 /r`	SSE2

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Element-wise: each word of the result comes from the word in the same place in each source.

Every word works alike: 4 and 8 words in the mm and xmm forms.

Result word i comes from word i of xmm1 and xmm2. Result words 7 to 0: r7, r6, r5, r4, r3, r2, r1, r0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

PCMPEQW mm, mm/m64

for i in range(4):
    a = mm1.w[i]
    b = src2.w[i]
    mm1.w[i] = -1 if a == b else 0
# x87: TOP = 0, all tags valid, bits 79:64 of mm1's register all ones

Run on AMD Zen 5 (EPYC 9645): 2 cases.

PCMPEQW xmm, xmm/m128

for i in range(8):
    a = xmm1.w[i]
    b = src2.w[i]
    xmm1.w[i] = -1 if a == b else 0
# bits 128 and up of the register are unchanged

Run on AMD Zen 5 (EPYC 9645): 2 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`PCMPEQW mm, mm/m64`
`mm`	explicit	read, write
`mm/m64`	explicit	read
`PCMPEQW xmm, xmm/m128`
`xmm`	explicit	read, write
`xmm/m128`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

PCMPEQW mm, mm/m64: mmx-mem
PCMPEQW xmm, xmm/m128: SSE_TYPE_4

Attributes

What else XED records about the forms. How to read.

PCMPEQW mm, mm/m64: may abort a TSX transaction
PCMPEQW xmm, m128: aligned memory operand

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to PCMPEQW, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`_mm_cmpeq_epi16` `__m128i _mm_cmpeq_epi16(__m128i __a, __m128i __b)`	`PCMPEQW xmm, xmm` Legacy -msse2
`_mm_cmpeq_pi16` `__m64 _mm_cmpeq_pi16(__m64 __m1, __m64 __m2)`	`PCMPEQW xmm, xmm` Legacy -msse2

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`PENTIUMMMX` MMX	MMX `CPUID.01H:EDX[23]` MMX	Every x86-64 processor in XED’s model and Zen 3 to Zen 6
`SSE2` SSE2	SSE2 `CPUID.01H:EDX[26]` SSE2	Every x86-64 processor in XED’s model and Zen 3 to Zen 6

More MMX instructions

All 47 MMX instructions

More SSE2 instructions

All 124 SSE2 instructions

Words in compiled code#