x86-64.net

Instruction

PCMPESTRI

Compares two strings of explicit lengths in EAX and EDX (RAX and RDX with REX.W) as an immediate says, returning an index in ECX.

Extensions
Forms
4 (4 Legacy)
Data
Intel XED v2026.08.23

PCMPESTRI is PCMPISTRI with explicit lengths: the same control byte, the same four comparisons and the same index in ECX, but the length of the pattern (the first operand) comes from EAX and that of the text (the second) from EDX, instead of ending each string at its first null. A null is then an ordinary element, so PCMPESTRI works on binary data and on strings whose length is known, as memchr and strspn on a counted buffer need. Its mask form is PCMPESTRM.

How the lengths are read

  • Each length is taken as a signed number and used by its absolute value: for EAX = -3 and EDX = -6 Zen 5’s result fits lengths of 3 and 6, both below 16, and EDX = -4 did not count as 0.
  • A length above 16 (8 for words) counts as 16: EDX = 17 compared the whole text, and ZF stayed clear.
  • Without REX.W only EAX and EDX are read, so the upper halves of RAX and RDX do not matter. With REX.W, PCMPESTRI64 reads RAX and RDX in full: Zen 5 took RDX = FFFFFFFF00000006H as the full length, 8 words in that case, where the plain form takes 6, and RAX = 8000000000000000H, whose absolute value does not fit, as a full 16 bytes.

The flags follow from the lengths: ZF is set when the text is shorter than 16 elements, SF when the pattern is, so a loop over a long buffer subtracts 16 from EDX each time and reads the end from ZF. CF and OF mean what they mean for PCMPISTRI.

Costs

Three registers are fixed, EAX, EDX and ECX, which compilers have to free around a loop. AMD’s Zen 5 guide lists PCMPESTRI as eight macro-ops with a register operand, one every three cycles, and twelve with memory, one every four; PCMPISTRI takes four, one every two cycles. Where a string ends at a null anyway, the implicit form is the cheaper one. Intel’s optimization manual describes both forms and their uses (Section 14.1).

From C, _mm_cmpestri(a, la, b, lb, mode) needs -msse4.2. GCC 14 and Clang 23 at -O2 move the two int lengths into EAX and EDX and emit the 32-bit form; Clang folds an unaligned load of the text into the instruction’s memory operand, which needs no alignment, while GCC loads it with MOVDQU first.

Forms

Every encoding of PCMPESTRI that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
PCMPESTRI xmm, m128, imm8 PCMPESTRI_XMMdq_MEMdq_IMMb66 0F 3A 61 /r ibSSE4.2
PCMPESTRI xmm, xmm, imm8 PCMPESTRI_XMMdq_XMMdq_IMMb66 0F 3A 61 /r ibSSE4.2
PCMPESTRI xmm, m128, imm8 64-bit mode only PCMPESTRI64_XMMdq_MEMdq_IMMb66 REX.W 0F 3A 61 /r ibSSE4.2
PCMPESTRI xmm, xmm, imm8 64-bit mode only PCMPESTRI64_XMMdq_XMMdq_IMMb66 REX.W 0F 3A 61 /r ibSSE4.2

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

All forms but the forms only in 64-bit mode
n = 8 if imm8 & 1 else 16  # words, bytes
w = 128 // n               # bits each
m = (1 << w) - 1
k = 1 << w - 1 if imm8 & 2 else 0  # signed
# the lengths: |EAX| and |EDX|, at most n,
# the count of imm8[0] (not of imm8[3])
la = min(abs(signed(eax)), n)
lb = min(abs(signed(edx)), n)
a = xmm1.read()
b = src2.read()
agg = imm8 >> 2 & 3
# (v >> w * i & m ^ k) - k: element i of v,
# sign-extended where k is its sign bit
r = 0
for j in range(n):     # bit j: src2's
    y = (b >> w * j & m ^ k) - k  # element j
    bit = 0
    if agg == 0:       # equal any: y is
        for i in range(la):  # in xmm1
            x = (a >> w * i & m ^ k) - k
            if j < lb and x == y:
                bit = 1
    elif agg == 1:     # ranges: y is in
        for i in range(0, la - 1, 2):
            t = w * i  # a pair's range
            lo = (a >> t & m ^ k) - k
            hi = (a >> t + w & m ^ k) - k
            if j < lb and lo <= y <= hi:
                bit = 1
    elif agg == 2:     # equal each
        x = (a >> w * j & m ^ k) - k
        if j < la and j < lb:
            bit = x == y
        else:          # 1 past both ends
            bit = j >= la and j >= lb
    else:              # equal ordered: xmm1
        bit = 1        # from element j on;
        # what would fall past the end of the
        # register matches, and an empty xmm1
        # everywhere, as in Intel's manual
        # (AMD's clears these bits)
        for i in range(min(la, n - j)):
            x = (a >> w * i & m ^ k) - k
            u = j + i
            z = (b >> w * u & m ^ k) - k
            if u >= lb or x != z:
                bit = 0
    r |= bit << j
p = imm8 >> 4 & 3
if p == 1:             # negated
    r ^= (1 << n) - 1
elif p == 3:           # negated within src2
    r ^= (1 << lb) - 1
idx = n                # none set
for j in range(n):     # imm8[6]: the
    if r >> j & 1:     # highest set bit,
        if imm8 & 0x40 or idx == n:
            idx = j    # else the lowest
ecx = idx              # bits 63:32 cleared
cf = r != 0
zf = lb < n            # src2 is short
sf = la < n            # xmm1 is short
of = r & 1
af = pf = 0

Run on AMD Zen 5 (EPYC 9645): 22 cases.

Forms only in 64-bit mode
n = 8 if imm8 & 1 else 16  # words, bytes
w = 128 // n               # bits each
m = (1 << w) - 1
k = 1 << w - 1 if imm8 & 2 else 0  # signed
# the lengths: |RAX| and |RDX| (REX.W), at
# most n, the count of imm8[0]
la = min(abs(signed(rax)), n)
lb = min(abs(signed(rdx)), n)
a = xmm1.read()
b = src2.read()
agg = imm8 >> 2 & 3
# (v >> w * i & m ^ k) - k: element i of v,
# sign-extended where k is its sign bit
r = 0
for j in range(n):     # bit j: src2's
    y = (b >> w * j & m ^ k) - k  # element j
    bit = 0
    if agg == 0:       # equal any: y is
        for i in range(la):  # in xmm1
            x = (a >> w * i & m ^ k) - k
            if j < lb and x == y:
                bit = 1
    elif agg == 1:     # ranges: y is in
        for i in range(0, la - 1, 2):
            t = w * i  # a pair's range
            lo = (a >> t & m ^ k) - k
            hi = (a >> t + w & m ^ k) - k
            if j < lb and lo <= y <= hi:
                bit = 1
    elif agg == 2:     # equal each
        x = (a >> w * j & m ^ k) - k
        if j < la and j < lb:
            bit = x == y
        else:          # 1 past both ends
            bit = j >= la and j >= lb
    else:              # equal ordered: xmm1
        bit = 1        # from element j on;
        # what would fall past the end of the
        # register matches, and an empty xmm1
        # everywhere, as in Intel's manual
        # (AMD's clears these bits)
        for i in range(min(la, n - j)):
            x = (a >> w * i & m ^ k) - k
            u = j + i
            z = (b >> w * u & m ^ k) - k
            if u >= lb or x != z:
                bit = 0
    r |= bit << j
p = imm8 >> 4 & 3
if p == 1:             # negated
    r ^= (1 << n) - 1
elif p == 3:           # negated within src2
    r ^= (1 << lb) - 1
idx = n                # none set
for j in range(n):     # imm8[6]: the
    if r >> j & 1:     # highest set bit,
        if imm8 & 0x40 or idx == n:
            idx = j    # else the lowest
ecx = idx              # bits 63:32 cleared
cf = r != 0
zf = lb < n            # src2 is short
sf = la < n            # xmm1 is short
of = r & 1
af = pf = 0

Run on AMD Zen 5 (EPYC 9645): 5 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.
OperandKindAction
PCMPESTRI xmm, xmm/m128, imm8
xmmexplicitread
xmm/m128explicitread
imm8explicitread
rAXimplicitread
rDXimplicitread
rCXimplicitwrite
RFLAGSimplicitwrite

Flags

M modified, 0 cleared; blank: not affected. How to read.
OFSFZFAFPFCF
All forms
MMM00M

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms
SSE_TYPE_4

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to PCMPESTRI, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

IntrinsicCompiles to
_mm_cmpestra int _mm_cmpestra(__m128i A, int LA, __m128i B, int LB, const int M)

PCMPESTRI xmm, xmm, imm8 Legacy -msse4.1 -msse4.2

_mm_cmpestrc int _mm_cmpestrc(__m128i A, int LA, __m128i B, int LB, const int M)

PCMPESTRI xmm, xmm, imm8 Legacy -msse4.1 -msse4.2

_mm_cmpestri int _mm_cmpestri(__m128i A, int LA, __m128i B, int LB, const int M)

PCMPESTRI xmm, xmm, imm8 Legacy -msse4.1 -msse4.2

_mm_cmpestro int _mm_cmpestro(__m128i A, int LA, __m128i B, int LB, const int M)

PCMPESTRI xmm, xmm, imm8 Legacy -msse4.1 -msse4.2

_mm_cmpestrs int _mm_cmpestrs(__m128i A, int LA, __m128i B, int LB, const int M)

PCMPESTRI xmm, xmm, imm8 Legacy -msse4.1 -msse4.2

_mm_cmpestrz int _mm_cmpestrz(__m128i A, int LA, __m128i B, int LB, const int M)

PCMPESTRI xmm, xmm, imm8 Legacy -msse4.1 -msse4.2

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.
ISA setCPUIDProcessors
SSE42

SSE4.2
CPUID.01H:ECX[20] SSE4.2

Nehalem, Westmere, Sandy Bridge, Ivy Bridge, Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Silvermont, Goldmont, Goldmont Plus, Tremont, Snow Ridge, Lakefield, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, K10 (Family 10h), Bulldozer, Piledriver, Zen, Zen+, Zen 2, Zen 3, Zen 4, Zen 5, Zen 6

Note: XED's AMD_K10 inherits everything from its Westmere chip, including SSSE3, SSE4.1, SSE4.2, AES-NI and PCLMULQDQ; GCC's -march=amdfam10 has none of them.

More SSE4.2 instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, operands, flags, exception classes, attributes, ISA sets, CPUID bits and chip model.
  2. The CPU data of x86-64.net: Zen 3 to Zen 6, from GCC’s -march feature sets and AMD’s Processor Programming References, which the page of each processor cites.
  3. Clang's x86 intrinsic headers, LLVM 23.1.2 (commit 85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them.
  4. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026): Volume 2B, page 4-254 (PCMPESTRI)
  5. AMD64 Architecture Programmer's Manual, Volume 4: 128-Bit and 256-Bit Media Instructions (26568, rev. 3.25, November 2021), Wayback Machine copy of AMD's PDF
  6. Intel 64 and IA-32 Architectures Optimization Reference Manual, Volume 1 (248966-051, October 2026)
  7. Software Optimization Guide for the AMD Zen5 Microarchitecture (58455, rev. 1.00, August 2024), Wayback Machine copy of AMD's ZIP

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang, part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.